Gate Electrode Crystal Orientation for Low-Resistance Memory Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices, such as scaled-down MOSFETs and three-dimensional NAND flash memories, face challenges in achieving low-resistance gate electrode layers to suppress gate delay and enhance speed, as existing materials and structures do not effectively orient crystal axes for optimal crystallinity and reduced electrical resistance.
Innovation Solution
The semiconductor device incorporates a gate electrode layer with a first conductive layer and a second conductive layer, both having their crystal axes oriented within specific ranges relative to the semiconductor layer, and an aluminum oxide insulating layer with specific crystal phases, enhancing crystallinity and reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate electrode layer structures are used, then manufacturing is simpler, but electrical resistance is high and gate delay increases
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate electrode layer by controlling crystal axis orientation within specific angular ranges (±10° or ±15°) and selecting specific crystal phases (α-aluminum oxide, θ-aluminum oxide) in the insulating layer to achieve low electrical resistance and suppressed gate delay
Solution Approach 2:
The patent uses composite material structures including multiple conductive layers (first conductive layer with first material, second conductive layer with second material) and insulating layers with specific crystal phases, where the combination and orientation of these materials work together to reduce electrical resistance while maintaining manufacturability
2Manufacturing precision
If crystal axis orientation is not controlled, then manufacturing is easier, but crystallinity is poor and electrical resistance increases
Solution Approach 1:
The patent specifies precise parameter ranges for crystal axis orientation (±10° or ±15° relative to the thickness direction) and crystal phase composition to achieve optimal crystallinity, balancing manufacturing precision requirements with ease of manufacture
Solution Approach 2:
The insulating layer containing aluminum oxide with specific crystal phases (α-aluminum oxide, θ-aluminum oxide) acts as an intermediary that promotes and maintains the crystal axis orientation of the underlying conductive layers, facilitating crystallinity improvement without requiring direct complex control of each layer
3Reliability
If standard insulating layers are used, then device structure is simpler, but leakage current is not minimized
Solution Approach 1:
The patent changes the insulating layer structure by incorporating aluminum oxide with specific crystal phases (α-aluminum oxide, θ-aluminum oxide) and controlling the thickness (5-20 nm) to minimize leakage current, while maintaining a relatively simple overall device structure
Solution Approach 2:
The patent applies local quality improvement by using aluminum oxide with specific crystal phases in the insulating layer at critical interfaces, where the local crystal structure and composition are optimized to minimize leakage current without requiring complex modifications throughout the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the crystallinity of the metal and barrier metal layers, reduces electrical resistance, and minimizes leakage current, thereby enhancing the performance and efficiency of the semiconductor device.
Implementation Method 1
the aluminum oxide including at least one crystal phase selected from a group consisting of α (alpha)-aluminum oxide and θ (theta)-aluminum oxide. The direction of the crystal axis of the aluminum oxide in the first insulating layer falls within a range of ±10° with respect to a first direction from the semiconductor layer toward the gate electrode layer
Implementation Method 2
both having their crystal axes oriented within specific ranges relative to the semiconductor layer, and an aluminum oxide insulating layer with specific crystal phases, enhancing crystallinity and reducing electrical resistance
Data Source
AI summary
A semiconductor device of embodiments includes: a semiconductor layer; a gate electrode layer including a first conductive layer containing a first material and a second conductive layer between the first conductive layer and the semiconductor layer and containing a second material different from the first material; and a first insulating layer between the semiconductor layer and the gate electrode layer and containing aluminum oxide, the aluminum oxide including α (alpha)-aluminum oxide or θ (theta)-aluminum oxide. The direction of the crystal axis of the aluminum oxide falls within a range of ±10° with respect to a first direction from the semiconductor layer toward the gate electrode layer. The direction of the crystal axis of the first material falls within a range of ±10° with respect to the first direction. The direction of the crystal axis of the second material falls within a range of ±10° with respect to the first direction.