Gate Cut Strain Engineering for Dense NMOS and PMOS Layouts
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Solution Overview
Problem
As integrated circuits scale downward in size, challenges arise in reducing device spacing and material stress on semiconductor channels impact device performance, particularly in forming semiconductor devices with non-planar transistors like finFETs and gate-all-around transistors, leading to complex processes and lower device yield.
Innovation Solution
Implementing gate cuts with compositionally different dielectric materials, such as silicon dioxide for compressive stress and silicon nitride for tensile stress, between adjacent transistor devices to enhance performance by confining the gate cuts within the gate trench and forming them before the gate structure, thereby improving stress management and device yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are packed more densely to reduce device size, then device density increases, but material stress control becomes more difficult and device performance deteriorates
Solution Approach 1:
The patent applies different dielectric materials with distinct mechanical properties to specific locations within the gate structure. Soft dielectric material (e.g., silicon oxide) is placed in regions requiring tensile stress on the channel, while hard dielectric material (e.g., silicon nitride) is placed in regions requiring compressive stress. This local differentiation of material properties enables precise stress control in densely packed devices without compromising performance.
Solution Approach 2:
The gate dielectric is constructed as a composite structure combining multiple dielectric materials with different mechanical characteristics. This composite approach allows the gate to simultaneously apply both tensile and compressive stress to different portions of the semiconductor channel, optimizing carrier mobility for both n-type and p-type transistors in compact configurations.
2Reliability
If different dielectric materials are used in gate cuts to apply stress, then transistor performance improves, but process complexity increases
Solution Approach 1:
The patent combines the formation of multiple dielectric layers with the gate cut etching process. By performing the gate cut to expose the semiconductor channel and then sequentially depositing different dielectric materials in a single integrated process flow, the methodology reduces the number of separate fabrication steps compared to forming separate stress application structures.
Solution Approach 2:
The gate cut is formed preliminarily before gate electrode deposition, exposing the semiconductor channel surface. This preliminary action allows subsequent dielectric materials to be deposited directly onto the channel region, establishing stress conditions early in the process and simplifying later fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The technique improves transistor performance by enhancing electron and hole mobility through targeted stress application, reducing process complexity, and increasing device yield in densely packed integrated circuits.
Implementation Method 1
The first dielectric material imposes a compressive stress on the first gate structure, and the second dielectric material imposes a tensile stress on the second gate structure
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
Techniques are provided herein to form semiconductor devices that include one or more gate cuts having materials that impose either a compressive or tensile stress on the adjacent semiconductor devices to improve performance. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut is confined within the gate trench. A first gate cut is arranged between adjacent NMOS devices and includes a dielectric material that imposes a tensile stress on the NMOS devices, and a second gate cut is arranged between adjacent PMOS devices and includes a dielectric material that imposes a compressive stress on the PMOS devices.