Self-Aligned Gate-Cuts With Sloped Sidewalls For Transistor Isolation
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Solution Overview
Problem
The challenge in semiconductor device technology is to form gate-cuts between transistor structures without misalignment, which can damage adjacent transistors or affect their performance, especially as transistor density increases and device dimensions shrink.
Innovation Solution
The solution involves forming self-aligned gate-cuts with sloped sidewalls on a sacrificial spacer, ensuring adequate spacing from adjacent transistors to prevent damage and misalignment issues. This technique allows for the formation of gate-cuts with concave or convex sidewalls, which can be more effectively aligned with stacked transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-cuts are formed between transistor structures, then electrical isolation between adjacent transistors is achieved, but misalignment during gate-cut formation can damage adjacent transistors or affect their performance
Solution Approach 1:
A sacrificial spacer is formed on the substrate before forming the gate-cut. This spacer is positioned at a first location away from the adjacent transistor structure, providing a pre-established reference feature that guides subsequent gate-cut formation. By preparing this spacer in advance, the gate-cut can be self-aligned to the spacer, preventing misalignment and damage to the adjacent transistor while ensuring proper electrical isolation.
Solution Approach 2:
The sacrificial spacer acts as an intermediary element between the substrate and the gate-cut. It is formed at a safe distance from the adjacent transistor, then used as a template or guide for forming the gate-cut. This intermediary structure enables precise positioning of the gate-cut without requiring direct alignment with the vulnerable transistor structure, thus preventing damage while achieving the necessary electrical isolation.
2Quantity of substance
If transistor density increases and device dimensions shrink, then integration capacity is improved, but alignment precision requirements become more stringent
Solution Approach 1:
The sacrificial spacer is formed in advance at a larger dimension (first location) that is easier to define with standard lithography processes. This pre-formed spacer serves as a robust alignment reference that can accommodate the reduced dimensions of high-density transistor structures, enabling precise gate-cut formation without requiring ultra-precise direct alignment to the small transistor features.
Solution Approach 2:
The gate-cut formation process uses the sacrificial spacer as a self-aligned reference, eliminating the need for separate alignment steps. The spacer's position and dimensions are designed such that the gate-cut automatically forms at the correct location relative to the adjacent transistor, providing self-correction against alignment errors and enabling high-density integration with maintained precision.
Data Source
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AI summary
Transistor devices (100) are provided. A transistor device (100) includes a substrate (110) and a transistor stack (101) on the substrate (110). The transistor stack (101) includes a lower transistor (Tb) and an upper transistor (Ta) that is on top of the lower transistor (Tb). Moreover, the transistor device (100) includes a gate-cut on the substrate (110), adjacent the transistor stack (101). The gate-cut has a first sloped sidewall and a second sloped sidewall that is opposite the first sloped sidewall. Related methods of forming transistor devices (100) are also provided.