Semiconductor Gate Dielectric Layout for Low-Capacitance CFET Stacks
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Solution Overview
Problem
Existing semiconductor structures face challenges in achieving high density, low parasitic capacitance, and high-frequency operation in field effect transistors (FETs), particularly in stacked configurations like CFETs.
Innovation Solution
A method for forming a semiconductor structure involves creating a layer stack with alternating sacrificial layers, removing select layers to form cavities filled with dielectric material, and applying different dielectric materials to achieve low parasitic capacitance and high-frequency operation, using techniques like atomic layer deposition (ALD) and chemical vapor deposition (CVD) to ensure precise dielectric placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric material is used to electrically insulate FETs in stacked configurations, then electrical insulation between FETs is improved, but parasitic capacitance increases which limits high-frequency operation
Solution Approach 1:
The patent applies different dielectric materials with different properties in different locations: a first dielectric material (e.g., silicon nitride) is used for vertical insulation between stacked FETs where high breakdown voltage is needed, while a second dielectric material (e.g., silicon oxide or low-k material) is used for horizontal insulation around gate structures where low parasitic capacitance is critical. This local differentiation allows simultaneous optimization of both insulation reliability and frequency performance.
2Productivity
If FETs are stacked densely to increase device density, then productivity and integration density are improved, but parasitic capacitance between adjacent FETs increases
Solution Approach 1:
Different dielectric materials are strategically placed in different regions: the first dielectric material fills vertical cavities between stacked FETs for compact integration, while the second dielectric material forms horizontal isolation layers and gate surrounds. This spatial differentiation enables dense stacking while controlling parasitic capacitance through material selection - high-k materials vertically for insulation, low-k materials horizontally for capacitance reduction.
Solution Approach 2:
The patent employs a composite dielectric structure combining multiple materials with complementary properties. The first dielectric material (silicon nitride or similar) provides high breakdown strength for vertical isolation, while the second dielectric material (silicon oxide or low-k material) provides low parasitic capacitance for horizontal isolation. This composite approach allows the structure to simultaneously achieve high device density and low parasitic effects.
3Ease of manufacture
If conventional single dielectric material is used for insulation, then manufacturing process is simple, but cannot simultaneously achieve low parasitic capacitance and high breakdown voltage
Solution Approach 1:
The patent changes the dielectric parameter (dielectric constant and breakdown strength) by using different materials in different locations. The first dielectric material has high breakdown strength (e.g., silicon nitride with ~10 MV/cm) for vertical insulation, while the second dielectric material has low dielectric constant (e.g., low-k material with k<3) for reducing parasitic capacitance. This parameter differentiation allows simultaneous optimization of insulation reliability and frequency performance.
Solution Approach 2:
The patent employs a composite dielectric structure combining multiple materials with complementary properties. The first dielectric material (silicon nitride or similar) provides high breakdown strength for vertical isolation, while the second dielectric material (silicon oxide or low-k material) provides low parasitic capacitance for horizontal isolation. This composite approach allows the structure to simultaneously achieve high device density and low parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables densely packed FETs with reduced parasitic capacitance, facilitating faster and higher frequency operation by optimizing dielectric materials and deposition methods.
Implementation Method 1
depositing a first dielectric material. Depositing the first dielectric material comprises filling the at least one cavity with the first dielectric material
Implementation Method 2
depositing a second dielectric material on the dielectric free gate surface. The second dielectric material is different from the first dielectric material. Depositing the second dielectric material is performed after depositing the first dielectric material
Data Source
AI summary
A method for forming a semiconductor structure includes forming a layer stack. The method also includes forming a gate structure on the layer stack, and forming at least one cavity by removing the at least one second sacrificial layer of the layer stack. The method further includes depositing a first dielectric material, and filling the at least one cavity with the first dielectric material. Further, the method includes providing a dielectric free gate surface, free from the first dielectric material. Furthermore, the method includes depositing a second dielectric material on the dielectric free gate surface. The second dielectric material is different from the first dielectric material.