Gate Dielectric Layer Uniformity in HV LV Integration
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Solution Overview
Problem
The integration of high voltage and low voltage devices on the same chip leads to non-uniformity in the thickness of the gate oxide layer, causing electrical issues and reliability problems due to 'gate oxide thinning' and junction leakage, which affects the device's stability and power consumption.
Innovation Solution
A method is developed to form a gate dielectric layer by first creating a thicker dielectric layer in the high-voltage circuit region, followed by forming trenches and an isolation layer, which includes a liner oxide layer to prevent thinning and depression, thereby ensuring uniformity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker gate oxide layer is formed in high voltage devices, then breakdown voltage is improved, but non-uniformity in thickness occurs causing gate oxide thinning
Solution Approach 1:
A liner oxide layer is formed on the sidewalls of the trench before filling it with isolation oxide. This preliminary action creates a protective layer that prevents the gate oxide from thinning during subsequent processing steps, ensuring uniform thickness while maintaining the required breakdown voltage.
Solution Approach 2:
The liner oxide layer acts as an intermediary between the trench sidewall and the gate oxide layer. It prevents direct contact and potential thinning effects, ensuring that the gate oxide maintains uniform thickness even in the presence of the trench structure.
2Ease of manufacture
If wet etching is used to remove mask layer and pad oxide, then ease of manufacture is improved, but erosion of silicon oxide layer occurs forming divots
Solution Approach 1:
The liner oxide layer is formed on the trench sidewalls before the wet etching step. This preliminary protective layer is resistant to the wet etching solution, preventing erosion and divot formation while allowing the etching process to proceed easily.
Solution Approach 2:
The liner oxide layer serves as an intermediary protective barrier between the wet etching solution and the silicon oxide layer. It withstands the chemical attack of the etching solution, preventing direct erosion of the underlying oxide and maintaining sidewall uniformity.
3Ease of operation
If the same oxide material is used for both isolation layer and gate oxide, then material consistency is improved, but junction leakage occurs due to depression formation
Solution Approach 1:
The liner oxide layer is formed on the trench sidewalls before filling with isolation oxide. This creates a protruding structure at the trench opening that prevents depression formation when the gate oxide is later removed from low voltage regions, eliminating the root cause of junction leakage.
Solution Approach 2:
The liner oxide layer acts as an intermediary structural element that modifies the geometry at the trench opening. Its protruding shape prevents the formation of depressions that would otherwise lead to junction leakage, while maintaining material consistency with the isolation layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents gate oxide thinning and depression, enhancing the reliability and stability of the device, reducing power consumption, and increasing operating speed by minimizing junction leakage.
Implementation Method 1
an isolation layer is formed on the substrate to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer
Implementation Method 2
a first dielectric layer serving as gate oxide layer in the high voltage circuit region is formed on the substrate
Data Source
AI summary
A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A mask layer is formed over the first dielectric layer. The mask layer, the first dielectric layer and the substrate are patterned to form trenches in the substrate. An isolation layer is formed to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer. The first dielectric layer of the low voltage circuit region is removed to expose the surface of the substrate. A second dielectric layer having a thickness smaller than the first dielectric layer is formed on the substrate in the low voltage circuit region.