Gate Dielectric Recess Layout for High-Voltage CMOS Integration
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Solution Overview
Problem
The integration of high voltage devices with low voltage devices in semiconductor integrated circuits poses challenges, particularly in system-on-chip technology, due to issues like punch-through and increased leakage, which degrade device reliability and require complex processing flows.
Innovation Solution
A semiconductor structure and fabrication method that includes forming a high voltage MOS device with a resist protective oxide layer having recesses between the drain region and the gate structure, filled with conductive material to reduce voltage breakdown and enhance operating bandwidth, while maintaining low conductive resistance and compatibility with CMOS process flows for both high voltage and logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high voltage devices are integrated with low voltage devices in SoC technology, then system functionality is improved, but device reliability deteriorates due to punch-through and leakage problems
Solution Approach 1:
The patent segments the semiconductor device into distinct high voltage and low voltage regions, with separate well structures (first well for high voltage, second well for low voltage) and independent gate structures. This segmentation allows each region to be optimized for its specific voltage requirements while preventing harmful interactions such as punch-through between regions, thereby maintaining reliability while achieving functional integration.
Solution Approach 2:
The patent applies local quality by providing different structural characteristics to different regions: the high voltage region has a first gate structure with specific dimensions and doping profiles optimized for high voltage operation, while the low voltage region has a second gate structure optimized for low voltage logic operation. This localized optimization allows each region to perform its function reliably without compromising the other.
2Reliability
If high implantation concentration is used to prevent punch-through and reduce source-drain resistance, then device performance is improved, but leakage increases and reliability degrades
Solution Approach 1:
The patent implements local quality by creating different doping concentration profiles in different regions. The high voltage region uses higher implantation concentration to prevent punch-through and reduce resistance, while the low voltage region uses lower concentration to minimize leakage. The separate well structures confine the high concentration doping to where it is needed, preventing leakage propagation to low voltage circuits.
3Adaptability or versatility
If complex processing flows are used to integrate high voltage and low voltage devices, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the fabrication processes for high voltage and low voltage devices into a unified process flow. Both device types share common processing steps including well formation, gate structure formation, and interconnect fabrication, while incorporating region-specific steps only where needed. This merging reduces the overall processing complexity compared to fabricating high voltage and low voltage devices separately while maintaining full functionality.
Data Source
AI summary
A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.