Gate-to-Drain Via Layout for Compact SRAM Routing
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Solution Overview
Problem
Static random-access memory (SRAM) area reduction is increasingly difficult in advanced technology nodes due to complex gate-to-drain connections, which complicate manufacturing and increase processing complexity.
Innovation Solution
Incorporation of an L-shaped middle via for gate-to-drain connection, allowing for the removal of a sacrificial gate and nanostructure channels, and the formation of a dielectric replacement layer to reduce SRAM area, relax gate isolation, and simplify routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional gate-to-drain connections are used in advanced technology nodes, then manufacturing complexity increases and processing becomes more difficult, but SRAM area reduction becomes increasingly difficult
Solution Approach 1:
The patent introduces an L-shaped middle via that extends in both vertical and lateral directions, transitioning from a conventional vertical via to a three-dimensional structure. This L-shaped via connects the gate contact to the drain contact by extending laterally beneath the gate structure and then vertically to reach the drain, thereby reducing overlay complexity while optimizing area utilization through spatial reconfiguration
Solution Approach 2:
The L-shaped middle via acts as an intermediary structure that mediates the connection between gate and drain contacts. By introducing this intermediate via structure with both lateral and vertical portions, the patent simplifies the routing path and reduces the overlay precision requirements compared to direct gate-to-drain connections, while simultaneously enabling more compact SRAM cell layout
2Area of stationary object
If L-shaped middle via is used for gate-to-drain connection, then SRAM area is reduced and routing is simplified, but via structure complexity increases
Solution Approach 1:
The L-shaped middle via is segmented into two distinct portions: a lateral portion that extends beneath the gate structure and a vertical portion that connects to the drain contact. This segmentation allows each portion to be optimized independently for its specific function, with the lateral portion providing horizontal routing and the vertical portion providing vertical connection, thereby managing complexity through functional decomposition
Solution Approach 2:
The L-shaped middle via structure embeds the lateral extension within the broader device layout, nesting the via path beneath existing gate structures. This nesting approach allows the via to utilize unused vertical and lateral spaces within the SRAM cell, achieving area reduction without adding external structural complexity to the overall device architecture
Data Source
AI summary
A device includes: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of first semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent the first stack; a first gate structure wrapping around the first stack and the second stack; a second gate structure wrapping around the third stack; a gate isolation structure between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally abutting the gate isolation structure; and a via. The via includes: a first portion that extends in a first direction, the first portion being on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion that extends in a second direction transverse the first direction.