Gate Driver Circuit to Block Leakage at the Control Node
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Solution Overview
Problem
In display devices, leakage currents from the control node of pull-down buffer transistors can cause the gate signal to rise when the display device is driven at low frequencies, leading to reduced reliability.
Innovation Solution
Incorporating an NMOS transistor between the input terminal and the control node in the gate driver stages, which prevents leakage currents during the self-scan period, maintaining the gate signal at a stable low voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the display device is driven at a low frequency, then power consumption is reduced, but leakage current causes the gate signal voltage to rise, reducing reliability
Solution Approach 1:
A seventh transistor (NMOS) is introduced as an intermediary component between the first transistor and the sixth transistor. This seventh transistor acts as a mediator to block leakage current paths, preventing the control node voltage from rising due to leakage during the self-scan period, thus maintaining gate signal stability at low driving frequencies
Solution Approach 2:
The seventh transistor is configured to preemptively block leakage current before it can affect the control node voltage. By positioning the NMOS transistor with its gate connected to the control node and its source/drain forming a current path between the first transistor and the sixth transistor, the circuit proactively prevents the harmful voltage rise that would otherwise occur during low-frequency operation
2Duration of action of moving object
If the pull-down buffer transistor is turned on for a long time, then the gate signal can be maintained at low voltage, but leakage current from the control node causes voltage rise, reducing reliability
Solution Approach 1:
The seventh transistor serves as an intermediary that blocks the leakage current path from the control node during extended on-periods. This allows the pull-down buffer transistor to remain on for long durations without accumulating leakage charge that would raise the control node voltage and compromise signal integrity
Solution Approach 2:
The invention changes the electrical parameters of the control node by introducing the seventh transistor, which modifies the leakage current characteristics. This parameter change enables the control node to maintain stable voltage levels even when the pull-down buffer transistor operates for extended periods at low driving frequencies
Data Source
AI summary
A gate driver includes a plurality of stages. Each of the plurality of stages includes a first transistor which transmits an input signal to a control node, a second transistor including a gate connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal connected to an output node from which a gate signal is output, a third transistor including a gate connected to the control node, a first terminal which receives a low gate voltage or a clock signal, and a second terminal connected to the output node, and a fourth transistor, which is an NMOS transistor, connected between a terminal of the first transistor and the gate of the sixth transistor, including a gate which receives a global signal having the high gate voltage in an address scan period and the low gate voltage in a self-scan period.