Gate Driver Overcurrent Detection via Blank Period Clock Phase

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Solution Overview

Problem

Display panels are prone to malfunction and risk of wiring burnout due to overcurrent issues, particularly when short circuits occur between driving voltage wirings, which existing technologies fail to adequately detect and prevent.

Innovation Solution

A display device with a driving circuit that includes a signal controller, voltage generator, and overcurrent detection circuit, which generates synchronized active and blank clock signals with distinct phase differences and voltage levels to detect overcurrents during the blank period, activating an overcurrent detection signal when a threshold is exceeded, thereby stopping driving voltage generation to prevent damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If overcurrent detection is performed continuously during active period, then detection precision is improved, but device complexity increases and power consumption increases

Engineering Contradiction:
Improveovercurrent detection precisionVSAvoiddetection circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing overcurrent detection during the blank period before the active period begins. The detection circuit checks for overcurrent conditions in advance (during blank period) and prepares protection measures before the high-current active period starts, preventing damage before it occurs rather than detecting it during operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic action by restricting overcurrent detection to specific time intervals (blank periods) rather than continuously during the entire operating cycle. The detection is performed periodically at the beginning of each frame's blank period, reducing computational burden and power consumption while maintaining effective monitoring

Inventive Principle:
Principle #19Periodic action

2Productivity

If phase difference between clock control signals is reduced in active period, then productivity is improved, but reliability deteriorates due to increased overcurrent risk

Engineering Contradiction:
Improvedata driving speedVSAvoidovercurrent protection reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies dynamics by making the phase difference between clock control signals variable rather than fixed. During the active period, the phase difference is reduced to enable faster data driving. During the blank period, the phase difference is increased to enable safe overcurrent detection. This dynamic adjustment of timing parameters optimizes both productivity and reliability

Inventive Principle:
Principle #15Dynamics

3Reliability

If blank period is extended for overcurrent detection, then reliability is improved, but loss of time increases

Engineering Contradiction:
Improveovercurrent detection reliabilityVSAvoidactive display time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies parameter changes by modifying the duration and timing of the blank period to accommodate overcurrent detection. The blank period is extended just enough to allow completion of detection operations, and the phase differences are adjusted to maximize the usable detection window without significantly impacting the active display time

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11087691B2Display device and a method of driving a gate driver
Publication Date: 2021.08.10 SAMSUNG DISPLAY CO LTD
  • US11087691B2 patent drawing
  • US11087691B2 patent drawing
  • US11087691B2 patent drawing

AI summary

A display device includes: a display panel including data lines, gate lines, and pixels, the display panel is operated in an active period or in a blank period; and a driving circuit for driving the display panel, the driving circuit including: a signal controller for outputting clock control signals; a voltage generator for receiving the clock control signals, wherein the voltage generator outputs active clock signals synchronized with the clock control signals during the active period and outputs blank clock signals during the blank period; and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, the overcurrent detection circuit detects an overcurrent of the blank clock signals, and a phase difference between the clock control signals in the active period is different from a phase difference between the clock control signals in the blank period.