Gate Driver Clock Control for Faster Scan Signal Fall Time
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Solution Overview
Problem
Existing display devices face challenges in reducing the falling time of scan signals, leading to potential overlap and deterioration of display quality due to RC delays in scan signals.
Innovation Solution
Incorporating a clock controller that connects the scan clock line to a power line in response to a carry clock signal, utilizing a switching transistor with an oxide semiconductor to rapidly pull down the scan clock signal, and employing a dummy stage to manage carry signals without outputting scan signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional gate driver is used without additional control circuits, then the device complexity is low, but the falling time of scan signals is prolonged leading to signal overlap and display quality deterioration
Solution Approach 1:
The patent introduces a clock controller as an intermediary component between the scan clock line and power line. This controller includes switching transistors that connect the scan clock line to the power line in response to carry clock signals, enabling rapid discharge of the scan clock signal and reducing the falling time of scan signals without requiring fundamental changes to the gate driver architecture
Solution Approach 2:
The patent employs dummy stages that generate carry clock signals in advance to trigger the clock controller before the actual scan signal needs to be pulled down. This preliminary action ensures that the scan clock line is ready to be rapidly discharged when needed, reducing signal overlap without adding complex control logic to each stage
2Manufacturing precision
If the scan signal falling time is reduced using aggressive design, then display quality improves, but manufacturing precision and reliability may deteriorate
Solution Approach 1:
The clock controller uses the existing carry clock signals from the gate driver stages themselves to control the switching transistors. The carry clock signals naturally provide the timing information needed to pull down the scan clock line, eliminating the need for external control circuits and reducing reliability concerns associated with additional control logic
Solution Approach 2:
The patent changes the electrical parameters of the scan clock line by dynamically connecting it to the power line through switching transistors. This parameter change allows the scan clock signal to be rapidly discharged from high voltage to low voltage, achieving precise timing control and reduced falling time while maintaining signal integrity through controlled transitions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the falling time of scan signals, minimizing signal overlap and enhancing display quality by ensuring timely transition to the gate-off voltage.
Implementation Method 1
a clock controller configured to connect the scan clock line to a power line in response to the carry clock signal
Implementation Method 2
utilizing a switching transistor with an oxide semiconductor to rapidly pull down the scan clock signal
Data Source
AI summary
A display device includes: a display panel including pixels connected to scan lines; a gate driver including stages, a stage from among the stages being configured to: provide, as a carry signal, a carry clock signal of a carry clock line to a next stage from among the stages; and provide, as a scan signal, a scan clock signal of a scan clock line to a corresponding scan line from among the scan lines in response to a previous carry signal of a previous stage from among the stages; and a clock controller to connect the scan clock line to a power line in response to the carry clock signal, the power line being configured to provide a constant voltage.