Gate Driving Circuit Layout Area Reduction via Planar Region Arrangement
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Solution Overview
Problem
Existing gate driving circuits for LCDs occupy excessive layout area due to vertically stacked output buffer, level shifter, and low voltage circuit regions, which contradicts the industry's goal of minimizing layout area and reducing costs.
Innovation Solution
A gate driving circuit design where the first output buffer unit, level shifter, and low voltage circuit regions are arranged horizontally and vertically on a plane, allowing the level shifter and output buffer unit to share a well, thereby reducing the overall layout height and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the output buffer region, level shifter region, and low voltage circuit region are arranged vertically, then the circuit functionality is complete, but the layout area becomes excessively large
Solution Approach 1:
The patent transitions from a vertical stacking arrangement to a horizontal planar arrangement of circuit regions. Specifically, the output buffer unit, level shifter, and low voltage circuit are positioned adjacent to each other in the same plane rather than stacked vertically, effectively utilizing the horizontal dimension to reduce overall layout area while maintaining complete circuit functionality.
Solution Approach 2:
The patent combines multiple circuit regions (output buffer unit, level shifter, low voltage circuit) into a single integrated layout structure. By positioning these regions adjacent to each other in the same plane and sharing common boundaries, the design merges previously separate vertical blocks into a unified horizontal structure, reducing total area occupation.
2Length of stationary object
If the level shifter and output buffer unit are positioned separately, then signal transformation is reliable, but the layout height increases
Solution Approach 1:
The level shifter and output buffer unit are positioned adjacent to each other in the same plane, sharing a common boundary. This spatial merging reduces the vertical layout height while maintaining the functional separation needed for reliable signal transformation from low-voltage to high-voltage levels.
Solution Approach 2:
Instead of stacking the level shifter and output buffer unit vertically, the patent positions them horizontally adjacent to each other in the same plane. This dimensional change reduces layout height while preserving the functional integrity and reliability of signal transformation.
3Ease of manufacture
If vertical stacking is used for circuit regions, then signal flow is straightforward, but manufacturing cost increases due to larger area
Solution Approach 1:
The patent rearranges circuit regions from vertical stacking to horizontal positioning in the same plane. This dimensional change reduces the overall layout area, directly lowering manufacturing costs while the structured adjacent positioning maintains straightforward signal flow and does not significantly increase layout arrangement complexity.
Solution Approach 2:
The horizontal arrangement configuration serves multiple functions simultaneously: it reduces layout area for cost reduction, maintains signal flow integrity, and provides a scalable template for additional circuit channels. This multi-functional design approach improves ease of manufacture without proportionally increasing device complexity.
Data Source
AI summary
A gate driving circuit includes a first output buffer unit region, a level shifter region and a low voltage circuit region. The first output buffer unit region is formed on a plane and is utilized for setting a first output buffer unit. The level shifter region is formed on the plane for setting a level shifter, and includes a vertical region and a horizontal region connected to the vertical region. The vertical region and the first output buffer unit region are aligned in a horizontal direction of the plane. The horizontal region is beneath the vertical region and the first output buffer unit region. The low voltage circuit region is formed on the plane for setting a low voltage circuit, and is beneath the horizontal region. The low voltage circuit region and the horizontal region are aligned in a vertical direction of the plane.