Gate Electrode Planarization for Mixed FinFET and Planar MOSFET Integration
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Solution Overview
Problem
The integration of planar MOSFETs and FinFETs in semiconductor devices is hindered by the roughening of the gate electrode surface, making it difficult to form fine gate patterns due to the complexity of the fabrication process, particularly in achieving a smooth surface for both transistor types.
Innovation Solution
A semiconductor device fabrication method involving the deposition of a mask material, patterning to form projections, burying a device isolation insulating film, and planarizing the gate electrode material using the mask and isolation film as stoppers, allowing for the formation of both planar and FinFETs with a planarized gate electrode surface, enabling the creation of a fine gate pattern and reducing the depth of focus requirements in lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both planar MOSFET and FinFET are embedded in the same device, then device functionality is improved, but the gate electrode surface becomes roughened making fine gate pattern formation impossible
Solution Approach 1:
The semiconductor substrate is divided into a FinFET formation region and a planar MOSFET formation region. The FinFET region undergoes anisotropic etching to form vertical fins, while the planar MOSFET region maintains a flat surface. This spatial segmentation allows each transistor type to have its required surface topology while coexisting in the same device.
Solution Approach 2:
Different surface qualities are applied to different regions: the FinFET region has a rough, vertical fin structure that provides high surface area for gate control, while the planar MOSFET region maintains a smooth, flat surface suitable for conventional gate patterning. The mask material and device isolation insulating film are used locally to preserve these different surface qualities in their respective regions.
2Ease of manufacture
If a simple fabrication process is used to embed both planar MOSFET and FinFET, then manufacturing complexity is reduced, but the gate electrode material surface roughening prevents fine gate pattern formation
Solution Approach 1:
A mask material is deposited and patterned before gate electrode formation to define the FinFET and planar MOSFET regions. This preliminary patterning creates a template that guides subsequent anisotropic etching and material deposition, ensuring that the gate electrode material is deposited on properly prepared surfaces in each region before final gate patterning occurs.
Solution Approach 2:
The mask material serves as an intermediary structure that protects the planar MOSFET region during FinFET formation and provides a stopper during CMP processing. The device isolation insulating film acts as another intermediary that fills trenches and provides a planarization reference. These intermediary structures enable the coexistence of different surface topologies without requiring complex separate fabrication processes.
3Adaptability or versatility
If the gate electrode material is deposited over both FinFET and planar MOSFET regions, then device integration is achieved, but surface roughness increases requiring higher lithography depth of focus
Solution Approach 1:
The device is segmented into distinct FinFET and planar MOSFET regions that are processed differently. The FinFET region receives anisotropic etching to create vertical fins, while the planar MOSFET region remains flat. This segmentation allows the gate electrode material to be deposited over both regions while maintaining appropriate surface characteristics in each, reducing the overall lithography complexity compared to forcing a single structure type across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the fabrication process, allows for the formation of both planar and FinFETs with a planarized gate electrode, enhancing the resolution and uniformity of the gate pattern, and improves the reliability of the gate insulating film by reducing overetching and line edge roughness.
Implementation Method 1
depositing a mask material on a semiconductor substrate
Implementation Method 2
depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film
Data Source
AI summary
According to the present invention, there is provided a semiconductor device fabrication method, comprising:depositing a mask material on a semiconductor substrate;patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region;burying a device isolation insulating film in the trench;etching away a predetermined amount of the device isolation insulating film formed in the first region;etching away the mask material formed in the second region;forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection;depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film;planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region;depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; andpatterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.