Gate Electrode Polishing for Semiconductor Structure Residue Reduction
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Solution Overview
Problem
In semiconductor manufacturing, the introduction of a single diffusion break (SDB) isolation structure can lead to reduced device performance due to issues like residue formation and difficulty in removing gate electrode material, particularly because the isolation structure's hardness is affected by the acid environment created during polishing, causing it to protrude and hinder the removal of gate electrode material.
Innovation Solution
A method involving sequential polishing treatments using a metal polishing liquid followed by deionized water to remove the gate electrode material and isolate structure, where the first treatment uses an acid polishing liquid to reduce the isolation structure's hardness, allowing for effective removal of the gate electrode material and minimizing residue formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single diffusion break (SDB) isolation structure is introduced to prevent source-drain bridging, then source-drain bridging of adjacent transistors is prevented, but device performance is reduced due to residue formation and difficulty in removing gate electrode material
Solution Approach 1:
The polishing process is segmented into two distinct stages: first polishing with metal polishing liquid to remove gate electrode material, then second polishing with deionized water to remove isolation structure material. This segmentation allows each polishing stage to target specific materials selectively, preventing residue formation while maintaining the SDB isolation structure's bridging prevention function.
Solution Approach 2:
The polishing liquid type is changed between two stages: from acid-based metal polishing liquid to neutral deionized water. This parameter change in polishing liquid chemistry enables selective removal of different materials (gate electrode vs. isolation structure) and prevents the isolation structure from protruding, thereby eliminating residue formation while preserving device performance.
2Ease of manufacture
If metal polishing liquid is used to remove gate electrode material, then gate electrode material is effectively removed, but the isolation structure's hardness is reduced causing it to protrude and hinder removal of gate electrode material
Solution Approach 1:
The first polishing treatment with metal polishing liquid is performed as a preliminary action to remove the gate electrode material before the second polishing treatment. This preliminary removal exposes the isolation structure top surface, allowing the subsequent deionized water polishing to cleanly remove any protruding isolation structure material without the isolation structure interfering with gate electrode material removal.
Solution Approach 2:
The softening effect of acid polishing liquid on the isolation structure, which initially appears harmful as it causes protrusion, is converted into a benefit by performing the acid polishing first to remove gate electrode material, then using deionized water polishing to remove the now-softened isolation structure protrusions. The temporary hardness reduction facilitates complete material removal without residue.
3Manufacturing precision
If polishing treatment is performed to remove gate electrode material above the interlayer dielectric layer, then residue formation is reduced, but the isolation structure may be damaged due to its reduced hardness in acid environment
Solution Approach 1:
The polishing process is divided into two segmented stages with different polishing liquids: first polishing with metal polishing liquid for gate electrode material removal, then second polishing with deionized water for isolation structure cleanup. This segmentation ensures that the isolation structure is only exposed to acid environment briefly during the first stage, and the second stage with neutral deionized water removes any protrusions without causing further damage, thus maintaining structural integrity while achieving complete material removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the probability of gate electrode material residue on the interlayer dielectric layer, improving device performance by ensuring thorough removal and maintaining the structural integrity of the isolation structure.
Implementation Method 1
performing first polishing treatment on the gate electrode material using a metal polishing liquid
Implementation Method 2
performing second polishing treatment on the isolation structure using deionized water
Data Source
AI summary
A semiconductor structure and a method for forming same, the forming method including: providing a base, where a dummy gate structure is formed on the base, an interlayer dielectric layer is formed on the base the dummy gate structure exposes, and the interlayer dielectric layer exposes the top of the dummy gate structure; forming an isolation structure in the interlayer dielectric layer between adjacent dummy gate structures, where the isolation structure further extends into the base; after forming the isolation structure, removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer; filling a gate electrode material into the gate opening, where the gate electrode material further covers the top of the interlayer dielectric layer; and performing at least one polishing treatment to remove the gate electrode material above the top of the interlayer dielectric layer and retaining the gate electrode material in the gate opening as a gate electrode layer, where the step of the polishing treatment includes: performing first polishing treatment using a metal polishing liquid; and performing second polishing treatment using deionized water. With the second polishing performance, the probability of forming a residue of the gate electrode material on the top surface of the interlayer dielectric layer is reduced, thereby improving device performance.