Gate Electrode Positioning to Suppress Short-Circuit Defects

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Solution Overview

Problem

Miniaturization of semiconductor devices leads to a higher likelihood of short-circuit defects between gate electrodes in split-gate nonvolatile memory cells, particularly during the 'write' operation, due to damaged regions in the gate insulating film, which are exacerbated by thinner film thickness and voltage differences between control and memory gate electrodes.

Innovation Solution

The method involves forming gate electrodes such that their upper surfaces are closer to the semiconductor substrate than the damaged regions in the gate insulating film, ensuring electrical insulation and reducing the occurrence of short-circuit defects by controlling the thickness and positioning of the gate electrodes relative to the damaged areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the semiconductor device is miniaturized to perform operations at high speed, then productivity and operation speed are improved, but the likelihood of short-circuit defects between gate electrodes increases due to damaged regions in the gate insulating film

Engineering Contradiction:
Improvedata processing speedVSAvoidshort-circuit defect occurrence
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent removes the damaged region from the gate insulating film by selectively etching the insulating film in the region between adjacent gate electrodes. This extraction of the harmful damaged region eliminates the source of short-circuit defects while preserving the functional portions of the gate insulating film, thereby maintaining high-speed operation capability without the reliability penalty.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent identifies the damaged region in the gate insulating film as a harmful factor causing short-circuits, and converts this harmful presence into a beneficial process by using the damaged region as a guide for selective removal. The etching process targets specifically the damaged area, transforming the defect into a controlled modification that improves reliability without affecting device performance.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Use of energy by moving object

If the thickness of the oxide film is reduced to lower write/erase voltage, then energy consumption is reduced, but the gate insulating film becomes more susceptible to damage and short-circuits

Engineering Contradiction:
Improvewrite/erase voltageVSAvoidgate insulating film damage
Core Design Contradiction:
Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effect of thin film susceptibility to damage by selectively removing only the damaged portions. The thin oxide film structure is preserved where needed for low-voltage operation, while the damaged regions between gate electrodes are eliminated through selective etching, transforming the vulnerability into a targeted improvement.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent applies different treatments to different regions of the gate insulating film: the functional regions under gate electrodes maintain their thin structure for low-voltage operation, while the inter-gate regions undergo selective etching to remove damaged portions. This local differentiation allows simultaneous achievement of low energy consumption and high reliability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11037830B2Method of manufacturing semiconductor device
Publication Date: 2021.06.15 RENESAS ELECTRONICS CORP
  • US11037830B2 patent drawing
  • US11037830B2 patent drawing
  • US11037830B2 patent drawing

AI summary

After the step of polishing, a part of each of each gate electrode is removed such that the upper surface of each gate electrode is located closer than the damaged region formed in the gate insulating film located between the gate electrodes to the main surface of the semiconductor substrate in cross-section view. Thus, it is possible to suppress the occurrence of a short-circuit defect during the operation of the semiconductor device.