Gate Electrode Support for SOI Active Layer Isolation
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Solution Overview
Problem
As semiconductor integration density increases, conventional isolation methods become ineffective in preventing interference between adjacent devices, and the manufacturing of both bulk silicon and SOI devices on a single wafer is costly and complex due to separate processing requirements.
Innovation Solution
A semiconductor device structure featuring a stack structure with a gap-filling insulation layer and a gate electrode that supports an active layer pattern, allowing for the simultaneous formation of bulk silicon and SOI devices on a common substrate by forming a sacrificial layer, recessed isolation, and filling the void with an insulation layer, enabling efficient device isolation and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation methods (LOCOS or trench isolation) are used, then device isolation is provided, but adjacent semiconductor devices interfere with each other as integration density increases
Solution Approach 1:
A sacrificial layer is introduced as an intermediary element between the first and second active layers. This sacrificial layer enables the formation of a recessed isolation structure that provides effective isolation between adjacent devices, preventing interference while maintaining compatibility with high integration density requirements.
Solution Approach 2:
The isolation structure is segmented into multiple components: a first isolation layer, a recessed portion, and a second isolation layer filled in the recess. This segmented approach allows the isolation structure to extend deeper into the substrate, providing enhanced isolation effectiveness that conventional single-layer isolation methods cannot achieve.
2Reliability
If ion implantation is used to prevent latch-up, then some isolation is provided, but it becomes ineffective when distance between devices decreases beyond a certain point
Solution Approach 1:
The isolation approach transitions from a two-dimensional planar isolation (conventional LOCOS or trench isolation) to a three-dimensional recessed isolation structure. By creating a recess that extends vertically into the substrate and filling it with isolation material, the isolation effectiveness is enhanced in the depth dimension, allowing isolation to remain effective even when horizontal device spacing is reduced.
3Reliability
If separate processing is used for SOI structure and bulk silicon region, then each device type can be optimized, but manufacturing cost and complexity increase
Solution Approach 1:
The patent merges the processing of SOI devices and bulk silicon devices into a single integrated process flow. The recessed isolation structure is formed simultaneously for both device types using common processing steps, including the formation and removal of the sacrificial layer. This unified approach eliminates the need for separate processing lines while maintaining the ability to optimize each device type's performance.
Solution Approach 2:
The recessed isolation structure serves multiple functions: it provides isolation for SOI devices, enables bulk silicon device formation in the same region, and prevents interference between adjacent devices. The sacrificial layer methodology is universally applicable across different device types, allowing a single process to achieve multiple isolation and device formation objectives.
Data Source
AI summary
Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.