Gate Etch Bowing Prevention via Selective Protection Layers
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Solution Overview
Problem
The gate etch process in semiconductor devices, particularly in NAND flash memory devices, results in unnecessary etching of layers other than the etch targets, leading to bowing profiles on the sidewalls of the gate pattern, which can cause damage and affect the reliability of the semiconductor device fabrication.
Innovation Solution
A method is introduced where buffer layers are formed on the sidewalls of layers other than the etch targets to protect them during the gate etch process, using a combination of protection layers with different etch selectivities to prevent bowing by selectively etching the dielectric and conductive layers, and subsequent oxidation to compensate for any damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etch conditions are optimized for the etch target material, then etching precision is improved, but non-target layers are unnecessarily etched causing bowing profiles
Solution Approach 1:
A buffer layer is introduced as an intermediary substance between the etch target and the non-target layers. This buffer layer selectively protects non-target layers during the etch process, allowing the etch conditions to be optimized for the target material without causing bowing profiles on the sidewalls of non-target layers.
Solution Approach 2:
The buffer layer is formed on the sidewalls of non-target layers before the etch process begins. This preliminary protective action ensures that when the etch process is performed with optimized conditions for the target material, the non-target layers are already protected and will not suffer from unnecessary etching or bowing profiles.
2Reliability
If multiple protection layers with different etch selectivities are used, then protection effectiveness is improved, but process complexity increases
Solution Approach 1:
Different protection layers with different etch selectivities are applied to different regions or layers that require specific protection levels. This local differentiation ensures that each non-target layer receives the appropriate level of protection tailored to its specific vulnerability during the etch process, maximizing protection effectiveness while avoiding unnecessary complexity in areas that don't require it.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents bowing profiles on the sidewalls of the gate pattern, ensuring reliable semiconductor device fabrication by protecting non-target layers during etching and minimizing damage, thereby enhancing the precision and reliability of the gate formation process.
Implementation Method 1
A first etch process is performed to remove the exposed dielectric layer thereby exposing a part of the first conductive layer
Implementation Method 2
A second etch process is performed to remove the exposed first conductive layer
Implementation Method 3
subsequent oxidation to compensate for any damage
Data Source
AI summary
A method of forming a gate of a semiconductor device includes providing a semiconductor substrate over which a first conductive layer, a dielectric layer and a second conductive layer are formed. The second conductive layer is patterned to expose a part of the dielectric layer. A first protection layer is formed on sidewalls of the second conductive layer. A first etch process is performed to remove the exposed dielectric layer and to expose a part of the first conductive layer. A second protection layer is formed on sidewalls of the second conductive layer. A second etch process is performed to remove the exposed first conductive layer.