Wrap-Around Gate Inner Spacer Structure for Etch Damage Control
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Solution Overview
Problem
Current methods for forming wrap-around gate devices with inner spacers face challenges in device fabrication and performance, particularly due to etching processes that can damage the inner spacers, leading to issues with capacitance and leakage between gate structures and source/drain features.
Innovation Solution
A method for forming robust inner spacers by selectively recessing sacrificial layers and depositing multiple dielectric layers with varying dielectric constants to create a barrier that prevents etch damage and reduces parasitic capacitance, involving conformal deposition and selective etching of materials like silicon nitride and silicon oxynitride.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used for channel release and source/drain formation, then device fabrication can proceed, but the inner spacers are damaged leading to increased capacitance and leakage
Solution Approach 1:
A low-k dielectric material layer is deposited conformally over the inner spacers before etching processes. This cushioning layer protects the inner spacers from direct etch exposure, preventing damage that would otherwise increase capacitance and leakage between gate structures and source/drain features.
Solution Approach 2:
The low-k dielectric material acts as an intermediary barrier between the etching process and the inner spacers. This intermediate layer allows etching to proceed for channel release and source/drain formation while mediating the harmful effects of the etch on the inner spacer structure.
2Reliability
If inner spacers are formed to reduce capacitance and leakage, then electrical performance improves, but the spacers are vulnerable to damage during subsequent etching processes
Solution Approach 1:
The low-k dielectric material is deposited beforehand over the inner spacers to provide protective cushioning. This ensures that when subsequent etching processes are performed for source/drain formation, the inner spacers maintain their structural integrity and electrical performance characteristics.
Solution Approach 2:
A thin film of low-k dielectric material is conformally deposited over the inner spacers. This thin protective film maintains the compact structure while providing sufficient protection during fabrication, balancing electrical performance with manufacturing robustness.
3Reliability
If multiple dielectric layers with varying dielectric constants are deposited, then parasitic capacitance is reduced and etch damage is prevented, but device structure becomes more complex
Solution Approach 1:
Different dielectric materials with varying dielectric constants are strategically positioned in different locations. The low-k dielectric material is deposited conformally over specific regions to reduce parasitic capacitance where needed, while maintaining appropriate structural complexity management through targeted material placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and electrical performance of semiconductor structures by preventing etch damage to inner spacers and reducing parasitic capacitance, thereby improving gate control and leakage characteristics.
Implementation Method 1
the low-k dielectric material layer to reduce parasitic capacitance between gate structures and source/drain features
Implementation Method 2
conformal deposition and selective etching of materials like silicon nitride and silicon oxynitride
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes channel members disposed above a substrate, a gate structure wrapping around the channel members, inner spacers adjacent to the gate structure, and a source/drain feature abutting the channel members. One of the inner spacers includes a middle dielectric portion and a shield dielectric portion that covers surfaces of the middle dielectric portion. The dielectric constant of the shield dielectric portion is greater than the dielectric constant of the middle dielectric portion.