Gate-Last 3D Memory Fabrication Reducing Leakage Current
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Solution Overview
Problem
As semiconductor memory devices are scaled down, they face design and process challenges such as increased leakage current due to the 'gate-first' technique used in forming monolithic three-dimensional memory arrays, which affects the performance of reversible resistance-switching memory cells.
Innovation Solution
The implementation of a 'gate-last' process for forming monolithic three-dimensional non-volatile memory arrays, where reversible resistance-switching memory cells include a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer not commonly shared by a vertical stack of word lines, reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the 'gate-first' technique is used to form monolithic three-dimensional memory arrays, then the manufacturing process can be completed earlier in the fabrication sequence, but leakage current increases between vertically adjacent word lines
Solution Approach 1:
The patent inverts the conventional fabrication sequence by forming the semiconductor material layer (resistance-switching element) before forming the word lines, rather than forming word lines first. This 'gate-last' approach reverses the traditional 'gate-first' methodology, allowing the semiconductor layer to be continuously deposited across the substrate and then selectively removed or modified to form memory cells, thereby eliminating leakage current between adjacent word lines while maintaining fabrication efficiency
Solution Approach 2:
The patent segments the fabrication process into distinct stages: first forming the continuous semiconductor material layer, then forming word lines, and finally selectively removing or modifying portions of the semiconductor layer to create individual memory cells. This segmentation allows the word lines to be formed without compromising the integrity of the semiconductor layer, thereby preventing leakage current while maintaining process efficiency
2Quantity of substance
If process geometries are scaled down to reduce cost per bit, then manufacturing cost decreases, but design and process challenges increase
Solution Approach 1:
The patent changes the fundamental parameter of fabrication sequence (from gate-first to gate-last) to enable continued scaling. By inverting the process sequence, the methodology maintains better control over leakage current at smaller geometries, allowing cost reduction through scaling while managing the associated design and process challenges through improved process control
Solution Approach 2:
The patent transitions from a planar two-dimensional memory structure to a three-dimensional vertical structure with stacked word lines and bit lines. This dimensional change increases storage density (reducing cost per bit) while the gate-last process provides better control over the complex three-dimensional fabrication challenges
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 'gate-last' technique reduces leakage current between vertically adjacent word lines, enhancing the performance and efficiency of monolithic three-dimensional memory arrays by improving the formation of barrier modulated switching structures.
Implementation Method 1
memory cells that include reversible resistance-switching memory elements that may be set to either a low resistance state or a high resistance state
Implementation Method 2
The 'gate-last' technique reduces leakage current between vertically adjacent word lines
Data Source
AI summary
A method is provided that includes forming a dielectric material and a first sacrificial material above a substrate, forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material, forming a first hole in the second sacrificial material, the first hole disposed in a first direction, forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole, forming a second hole in the second sacrificial material, forming a second portion of the nonvolatile memory material on a sidewall of the second hole, forming a local bit line in the second hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.