Semiconductor Gate Layout With Oblique Tabs For HEIP Prevention

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Solution Overview

Problem

In high-integration DRAM devices, the miniaturization of transistor gates leads to significant degradation of transistor characteristics due to hot-electron-induced punch-through (HEIP) and field crowding effects, where the conventional method of attaching tabs to the gate edges to distribute electric current path is ineffective due to tab reduction during the patterning process.

Innovation Solution

A gate layout with a stepped side boundary in the active region is introduced, where tabs are arranged in an oblique direction to maintain sufficient spacing and prevent the connection of adjacent gates, eliminating the need for tab removal and ensuring the tabs maintain their size, thereby preventing HEIP and enhancing transistor characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If tabs are attached to gate edges to distribute electric current path, then HEIP prevention is improved, but tab size is reduced during patterning process

Engineering Contradiction:

ImproveHEIP preventionVSAvoidtab size

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent positions tabs in the oblique direction (at an angle) rather than directly adjacent to gates, changing the spatial arrangement from a one-dimensional linear layout to a two-dimensional angular layout. This dimensional change allows sufficient spacing between tabs while maintaining their effectiveness in distributing electric current paths and preventing HEIP, thereby preserving tab size during patterning.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the gate structure into separate components (gates and tabs) with spatial separation in the oblique direction. This segmentation prevents the formation of bridge portions between adjacent gates while maintaining the functional integrity of tabs for current path distribution, thus preserving manufacturing precision.

Inventive Principle:

Principle #1Segmentation

2Productivity

If gate length is reduced for high integration, then device miniaturization is improved, but transistor characteristic degradation worsens

Engineering Contradiction:

Improvedevice integrationVSAvoidtransistor characteristic

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies different structural characteristics to different regions: gates are miniaturized for high integration, while tabs are positioned in the oblique direction with sufficient spacing to maintain their current-distributing function. This local differentiation allows simultaneous achievement of device miniaturization and transistor characteristic reliability.

Inventive Principle:

Principle #3Local quality

3Productivity

If gate spacing is reduced for miniaturization, then device density is improved, but field crowding effect worsens

Engineering Contradiction:

Improvedevice densityVSAvoidfield crowing effect

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

By positioning tabs in the oblique direction rather than directly adjacent to gates, the patent creates sufficient spatial separation that prevents field crowding effects while maintaining high device density through compact gate spacing.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7432143B2Method for forming gate of semiconductor device

Publication Date: 2008.10.07 SAMSUNG ELECTRONICS CO LTD

AI summary

There is provided a method for forming a gate using a gate layout of a semiconductor device. The layout includes an active region with a stepped side boundary, a plurality of gates crossing over the active region, and tabs attached to the gates on the side boundary of the active region, wherein two tabs adjacent by a topology of the stepped side boundary are disposed in an oblique direction. The gates can be patterned.