Gate Leakage Reduction in Multi-Power-Domain CMOS Chips
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Solution Overview
Problem
Existing SOC chips face significant gate leakage currents when in sleep or standby mode, which shorten the battery life of devices powered by small batteries, as conventional methods to reduce leakage currents either increase power consumption or degrade circuit performance.
Innovation Solution
A circuit and method that utilize a logic ANDing circuit to apply a low voltage to the gate electrode of transistors in a switchable power domain when the power switch is open, reducing gate leakage currents by disabling them, and using HVT transistors in isolation cells to minimize leakage while maintaining high-speed performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power switch is opened to reduce power consumption in sleep mode, then energy consumption is reduced, but gate leakage current increases due to floating gate voltages
Solution Approach 1:
An intermediary circuit is introduced between the power switch and the transistor gates. This intermediary actively manages the gate voltages during power switching transitions, ensuring that gates are properly discharged to ground before the power switch opens, thereby preventing the harmful floating voltage condition that causes increased gate leakage current.
Solution Approach 2:
The patent applies preliminary action by discharging the transistor gates to ground voltage before opening the power switch. This preliminary discharge action prevents the accumulation of floating voltages that would otherwise occur when the power switch opens, thereby eliminating the condition that leads to increased gate leakage current in sleep mode.
2Device complexity
If conventional transistors are used in isolation cells, then circuit complexity is reduced, but gate leakage current increases significantly
Solution Approach 1:
The patent applies local quality by using different transistor types in different locations within the circuit. Specifically, HVT transistors are used in the isolation cell where low leakage is critical, while other parts of the circuit can use conventional transistors. This localized application of specialized components solves the leakage problem in the isolation cell without unnecessarily increasing complexity throughout the entire circuit.
3Object-generated harmful factors
If HVT transistors are used in isolation cells to reduce leakage, then gate leakage current is reduced, but circuit performance degrades
Solution Approach 1:
HVT transistors are used specifically in the isolation cell where low leakage is the primary requirement, while SVT transistors are used in the main logic path where high performance is required. This localized application allows the system to achieve low leakage in the isolation function without degrading the overall circuit performance.
Solution Approach 2:
The patent segments the circuit into different functional blocks with different performance requirements. The isolation cell is segmented as a separate functional unit with its own transistor type optimization, allowing it to be optimized for low leakage independently from the main logic circuitry that requires high performance.
4Speed
If SVT transistors are used to maintain high-speed performance, then circuit performance is maintained, but gate leakage current increases to microamperes
Solution Approach 1:
SVT transistors are used in the main logic path where high-speed performance is required, while HVT transistors are used in the isolation cell where low leakage is critical. This spatial differentiation allows each component to be optimized for its specific function without compromising overall system performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate leakage currents by up to 20 times, significantly extending the battery life of SOC chips and maintaining high-speed performance, particularly in low-power applications where the chip is often in sleep mode.
Implementation Method 1
The gate leakage currents ILEAKN and ILEAKP 'tunnel' across the gate oxides of N-channel transistor MN1 and P-channel transistor MN1, respectively, if the voltage between the gate electrode and the body electrode (i.e., the voltage across the gate oxide) is sufficiently high.
Data Source
AI summary
A circuit for reducing gate leakage current in a switchable power domain of a CMOS (complementary metal oxide semiconductor) integrated circuit chip includes a first transistor having a drain electrode coupled to a first terminal of a power switch having a second terminal coupled to a first reference voltage, the first transistor having a gate electrode, a body electrode, and a source electrode. The source electrode and body electrodes are coupled to a second reference voltage. The first transistor has a relatively high first gate leakage current that flows from its gate electrode to its body electrode if the power switch is open and a voltage of the gate electrode of the first transistor representing a first logic level exceeds a voltage of the body electrode by more than a first predetermined amount. A first circuit produces a relatively low voltage on the gate electrode of the first transistor representing a second logic level to substantially reduce the first gate leakage current when reduced power consumption of the chip is needed.