Gate-Level Simulation X-Pessimism Correction via Sub-Circuit Analysis
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Solution Overview
Problem
Gate-level logic simulation becomes inaccurate due to X-pessimism, where unknown values (Xs) are propagated, leading to false Xs and rendering simulations useless, especially with physical optimizations and low-power requirements.
Innovation Solution
The system identifies false Xs during simulation, traces the fan-in cone to find a sub-circuit responsible, and generates auxiliary code to eliminate these Xs, allowing for correct simulation results by replacing false Xs with their correct values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate-level simulation is performed with unknown values (Xs) present, then simulation coverage is improved, but simulation accuracy deteriorates due to X-pessimism propagating false Xs
Solution Approach 1:
The patent segments the simulation process into two distinct phases: a formal analysis phase that identifies false Xs by proving whether unknown values can be determined, and a gate-level simulation phase that uses this information to correct simulation accuracy. This segmentation allows the system to maintain both broad simulation coverage and high accuracy by applying different methods to different aspects of the simulation.
Solution Approach 2:
The patent introduces formal analysis as an intermediary component between the testbench and gate-level simulation. This intermediary analyzes the design netlist to identify false Xs and provides correction information to the simulation process, thereby mediating between the need for comprehensive simulation coverage and the requirement for accurate results.
2Reliability
If random values are deposited at registers to eliminate X problems, then false X propagation is reduced, but bugs may escape verification due to incomplete value representation
Solution Approach 1:
The patent implements a feedback mechanism where formal analysis results about false X identification are fed back into the gate-level simulation process. This feedback loop allows the simulation to be corrected based on proven information about which unknown values are actually false, thereby improving both X elimination effectiveness and bug detection accuracy without the limitations of random value deposition.
3Measurement precision
If formal analysis is applied during simulation to replace false Xs, then current false Xs are resolved, but subsequent false Xs are not resolved as the analysis is not generic
Solution Approach 1:
The patent performs preliminary formal analysis before gate-level simulation to identify all false Xs in advance. This preliminary action creates a comprehensive set of corrections that can be applied throughout the entire simulation process, ensuring that both current and subsequent false Xs are resolved without requiring repeated formal analysis during simulation.
Data Source
AI summary
This invention provides a system and method for correcting gate-level simulation commences by identifying unknown values (Xs) that are falsely generated during the simulation of a given trace for a design netlist. Then, a sub-circuit of the design netlist is determined for each false X that has inputs of real Xs and an output of a false X. Finally, simulation correction code is generated based on the sub-circuit to eliminate false Xs in simulation of the design netlist. The original design netlist can then be resimulated with the simulation repair code to eliminate false Xs. This allows gate-level simulation to produce correct results.