3D Memory Gate Line Isolation Structure
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Solution Overview
Problem
The challenge in the semiconductor industry is to overcome the limitations of 2D or planar NAND flashes, which face storage density constraints and increased manufacturing costs due to the difficulty in scaling down feature sizes.
Innovation Solution
A semiconductor structure is developed, featuring a first stack structure with alternating insulating and gate line layers, a second stack structure with a select gate line layer, and a gate line isolation structure penetrating through both stacks. This structure includes a first dielectric layer covering the gate line isolation structure and conductive posts connecting the channel structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D or planar NAND flash structure is used, then manufacturing process is simpler, but storage density approaches upper limit and feature size scaling becomes difficult
Solution Approach 1:
The patent transitions from 2D planar NAND structure to 3D vertical stack structure by stacking multiple insulating layers and gate line layers alternately in the vertical direction, enabling storage density improvement without further scaling feature sizes in the planar dimension
Solution Approach 2:
The structure is divided into multiple discrete layers (insulating layers and gate line layers) stacked alternately, with each layer serving specific functions, allowing independent optimization and manufacturing of each layer while achieving high overall density
2Quantity of substance
If feature size is scaled down to increase storage density, then storage capacity improves, but manufacturing difficulty and cost increase
Solution Approach 1:
Instead of continuing to scale feature sizes in the lateral dimension, the patent moves to vertical stacking to achieve higher storage density, avoiding the manufacturing difficulties associated with further feature size reduction
Solution Approach 2:
Multiple functional layers are nested vertically within each other, with insulating layers and gate line layers alternating in the vertical stack, allowing high density without requiring smaller lateral feature sizes
3Productivity
If gate line isolation structure is implemented, then manufacturing efficiency improves and defect risk reduces, but process complexity increases
Solution Approach 1:
The gate line isolation structure is formed preliminarily before subsequent fabrication steps, establishing isolation regions in advance to prevent defects and guide subsequent processing, improving overall manufacturing efficiency
Solution Approach 2:
The gate line isolation structure acts as an intermediary element that separates and isolates different gate line regions, preventing unwanted electrical interaction and simplifying the control of subsequent fabrication processes
Data Source
AI summary
The present disclosure provides a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a semiconductor layer, a first stack structure, a second stack structure, a gate line isolation structure, and a first dielectric layer. The first stack structure includes a plurality of first insulating layers and a plurality of gate line layers disposed alternatively. The second stack structure is disposed on a side of the first stack structure away from the semiconductor layer and includes a select gate line layer. The gate line isolation structure penetrates through the first stack structure and the second stack structure in a direction perpendicular to the semiconductor layer. The first dielectric layer is disposed on a side of the second stack structure away from the semiconductor layer, contacts the gate line isolation structure, and covers at least a part of a surface of the gate line isolation structure away from the semiconductor layer.