Gate Pattern Liner Recessing for Uniform Metal Silicide Thickness
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Solution Overview
Problem
Existing semiconductor device fabrication methods fail to achieve uniform thickness of metal silicide in the upper regions of gate patterns, leading to inconsistent device performance.
Innovation Solution
A method involving the formation of a liner insulating layer with a first thickness on gate patterns, followed by a gap fill layer using FCVD or SOG, and subsequent recessing to achieve a second thickness in desired regions, allowing for uniform metal silicide formation in these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional fabrication method is used to form metal silicide on gate patterns, then the metal silicide can be formed, but the thickness of the metal silicide is non-uniform in the upper regions of the gate patterns
Solution Approach 1:
The patent applies local quality by forming a liner insulating layer with spatially varying thickness: a first thickness in non-desired regions and a second thickness (smaller than the first) in desired upper regions of gate patterns. This localized thickness variation enables uniform metal silicide formation only in the desired regions, resolving the contradiction between thickness uniformity and device performance consistency.
Solution Approach 2:
The patent employs preliminary action by pre-forming the liner insulating layer with controlled thickness distribution before metal silicide formation. The gap fill layer is also formed in advance to define the desired upper regions. These preliminary structures guide the subsequent metal silicide formation process to achieve uniform thickness only where needed, improving both manufacturing precision and reliability.
2Ease of manufacture
If the liner insulating layer is formed with uniform thickness across the gate pattern, then the fabrication process is simple, but the metal silicide thickness becomes non-uniform in desired regions
Solution Approach 1:
The liner insulating layer is designed with local quality variations: a first thickness in non-desired regions and a second thickness in desired upper regions. This localized differentiation enables precise control over metal silicide formation, achieving uniform thickness in desired regions while maintaining reasonable fabrication complexity through standardized deposition processes.
Solution Approach 2:
The patent introduces thickness dimensionality variation in the liner insulating layer to control metal silicide formation. By varying the liner thickness in the vertical dimension across different spatial regions, the patent achieves precise control over metal silicide thickness uniformity without significantly complicating the overall fabrication process.
3Manufacturing precision
If the liner insulating layer thickness is reduced in desired regions, then uniform metal silicide can be formed, but additional process steps are required
Solution Approach 1:
The gap fill layer is formed in advance to define the desired upper regions of gate patterns. This preliminary structure serves as a template for subsequent liner insulating layer formation and metal silicide deposition, enabling precise thickness control without requiring complex real-time adjustments during metal silicide formation.
Solution Approach 2:
The liner insulating layer acts as an intermediary between the gate pattern and the metal layer. By controlling the liner thickness in desired regions, it mediates the metal silicide formation process to achieve uniform thickness. The gap fill layer serves as an intermediary structure to define the spatial regions where this control is applied.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the formation of metal silicides with relatively uniform thicknesses in the upper regions of gate patterns, enhancing device performance and consistency.
Implementation Method 1
a gap fill layer filling a gap between adjacent gate patterns may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD)
Implementation Method 2
A metal silicide may be formed using the metal layer. In particular, the upper regions of the plurality of gate patterns may be transformed into a metal silicide using the metal layer
Data Source
AI summary
Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.