Semiconductor Gate Metal Layout for Fracture-Resistant Strip Contacts
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Solution Overview
Problem
Conventional dual patterning technology struggles with the formation of fragile long and thin patterns in semiconductor devices, leading to fractures and reduced production yield.
Innovation Solution
A semiconductor structure and manufacturing method that splits metal layer patterns with high aspect ratios into two photolithography etching steps, considering both pattern density and length-width ratio, to enhance the quality and reduce fracture probability of strip contact structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional dual patterning technology is used to form metal layer patterns, then the manufacturing process can be completed, but the formed long and thin patterns are fragile and prone to fracture
Solution Approach 1:
The patent divides the formation of metal layer patterns into two separate photolithography etching steps instead of forming all patterns in a single step. This segmentation allows better control over the formation of long and thin patterns, reducing stress concentration and preventing fractures during the manufacturing process.
2Device complexity
If metal layer patterns are formed in a single photolithography etching step, then the manufacturing process is simpler, but the pattern quality and structural integrity deteriorate
Solution Approach 1:
The manufacturing process is segmented into two distinct photolithography etching steps: a first etching step for forming initial patterns, and a second etching step for forming the metal layer patterns. This segmentation enables precise control over pattern formation, ensuring high manufacturing precision and structural integrity of long and thin patterns.
3Reliability
If long and thin metal layer patterns are formed, then the electrical connection between gate structures is achieved, but the patterns become prone to fracture
Solution Approach 1:
The formation of long and thin metal layer patterns is divided into two etching steps, where the first step creates initial structures and the second step completes the metal layer formation. This segmented approach reduces stress accumulation and prevents fractures in long and thin patterns while maintaining electrical connectivity between gate structures.
Solution Approach 2:
The first photolithography etching step performs preliminary action by forming initial patterns and structures before the second step. This preliminary formation allows subsequent steps to complete the metal layer with reduced stress and improved structural strength, preventing fractures in long and thin regions.
Data Source
AI summary
The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.