3D Memory Gate Contact Plugs for Reliable Dense Stacking
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and integration density while maintaining reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor device design featuring a stack structure with vertically stacked gate layers, memory vertical structures, and conductive gap fill patterns with liner layers, along with specific contact plug configurations to enhance electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The device is divided into distinct functional regions: a first region containing vertically stacked memory cells with gate layers, and a second region containing peripheral circuits. This spatial segmentation allows independent optimization of each region, enabling high-density memory storage while maintaining manageable peripheral circuit complexity.
Solution Approach 2:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking. Multiple gate layers are stacked vertically above the bit line, creating a multi-layer memory structure that dramatically increases storage capacity per unit area by utilizing the vertical dimension.
2Manufacturing precision
If contact plugs are formed closer to gate layers to improve integration density, then integration density is improved, but electrical connectivity and reliability deteriorate
Solution Approach 1:
A liner layer is introduced as an intermediary between the contact plug and the gate layer. This liner layer serves multiple functions: it provides a diffusion barrier to prevent material intermixing, ensures good electrical contact, and maintains structural integrity. The contact plug is positioned adjacent to the gate layer while the liner layer mediates the interface, preserving both high integration density and reliable electrical connectivity.
Solution Approach 2:
The liner layer is applied selectively at the contact plug-gate layer interface where specific local requirements exist. This localized treatment provides enhanced electrical connectivity and structural stability precisely where needed, without affecting other regions of the device, thereby maintaining high integration density while improving reliability at critical interfaces.
Data Source
AI summary
A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.