Gate Profile Control via Directional Ion Beam Protection
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Solution Overview
Problem
Conventional gate etching processes in semiconductor manufacturing face challenges in achieving precise control over gate profiles, particularly in forming dense and iso regions, leading to issues with device performance and yield due to inadequate protection of gate foot portions during etching.
Innovation Solution
The implementation of a directional deposition process using a protection layer, formed by ion beam deposition, to selectively cover and shield specific sidewalls of gates, allowing for anisotropic etching without damaging the fin structure, and subsequent removal of unprotected foot portions to achieve vertical profiles in both dense and iso regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate etching process is used, then gate profiles can be formed, but fin structure loss occurs and manufacturing precision deteriorates
Solution Approach 1:
A protection layer is deposited as an intermediary between the etching process and the gate structure. This protection layer selectively shields the foot portions of gates in dense regions during etching, preventing fin structure loss while allowing the etch to proceed in iso regions. The protection layer acts as a mediator that enables precise gate profile formation without the harmful side effect of fin structure damage.
Solution Approach 2:
The protection layer is applied selectively to specific locations (foot portions of gates in dense regions) rather than uniformly across all gates. This local application allows the etching process to proceed differently in different regions: protected in dense regions to prevent fin loss, and unprotected in iso regions to allow proper etching. This spatially varying protection strategy resolves the contradiction between preventing fin loss and achieving precise gate profiles.
2Productivity
If high ion energy is used for etching, then etching speed increases, but gate foot portions become damaged
Solution Approach 1:
The protection layer is deposited before the etching process to preemptively shield the gate foot portions. This preliminary protective action allows the subsequent etching to use higher ion energy for faster processing without risking damage to the gate foot portions. The protection layer is removed after etching, leaving the gate with an intact vertical profile. This advance protection enables high-speed etching while maintaining precision.
3Object-affected harmful factors
If anisotropic etching is used to protect fin structure, then fin structure integrity is maintained, but gate profile precision deteriorates
Solution Approach 1:
The protection layer creates local quality differences in the etching process. In dense regions where protection layer is present, the etching is more conservative to maintain fin structure. In iso regions where protection layer is absent, the etching can be more aggressive to achieve precise gate profiles. This localized etching strategy, enabled by spatially selective protection layer deposition, resolves the contradiction between fin structure protection and gate profile precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures precise gate profiles, enhances device performance, and improves yield by preventing fin structure loss during etching, while allowing for isotropic etching with low ion energy, thereby maintaining the integrity of the semiconductor structure.
Implementation Method 1
depositing, by using an directional ion beam, a protection layer to wrap around a top surface, a first sidewall and a second sidewall of the first gate
Data Source
AI summary
A method includes forming a gate layer over a semiconductor fin; forming a patterned mask over the gate layer; performing a first etching process to pattern the gate layer using the patterned mask as an etch mask, the patterned gate layer comprising a first gate extending across the semiconductor fin; depositing, by using an directional ion beam, a protection layer to wrap around a top surface, a first sidewall and a second sidewall of the first gate, the protection layer extending along the first and second sidewalls of the first gate towards a bottom surface of the first gate without extending to the bottom surface of the first gate on the second sidewall of the first gate; and after depositing the protection layer, performing a second etching process to a portion of the second sidewall of the first gate exposed by the protection layer.