Gate Line Slit Layout for Stable 3D Memory Block Isolation
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Solution Overview
Problem
The increasing number of stacked layers in memory devices leads to instability in memory structures, particularly when manufacturing gate line slits, resulting in potential electrical connections between adjacent memory blocks and structural instability.
Innovation Solution
A semiconductor device fabrication method involving a stack with interlayer sacrifice layers and insulation layers, where a gate line slit is formed with interconnected slits of varying widths, including a first slit in the periphery region and a second slit in the core region, with an isolation section in the first slit to prevent interlayer sacrifice layers from being replaced with gate layers, thereby enhancing structural stability and separating memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate line slit is formed in the memory stack, then memory blocks can be separated, but structural instability occurs leading to potential collapse under external stress
Solution Approach 1:
The gate line slit is divided into multiple segments (first slit, second slit, third slit) with different widths rather than forming a single continuous slit. This segmentation allows the structure to be separated into memory blocks while maintaining structural integrity through the varying slit widths that provide mechanical support at different locations.
Solution Approach 2:
Different regions of the gate line slit have different widths tailored to their specific functional requirements. The first slit has a first width for optimal memory block separation, the second slit has a second width for structural support, and the third slit has a third width for transition region isolation. This local differentiation resolves the contradiction by providing both separation capability and structural stability where needed.
2Reliability
If the gate line slit width is increased to improve separation, then memory block isolation is enhanced, but fabrication precision requirements increase
Solution Approach 1:
The gate line slit is segmented into multiple sections with different widths, allowing each section to be optimized for its specific function. This segmentation enables achieving good memory block isolation in the first slit without requiring the entire slit structure to maintain uniform high precision, as other sections have different width requirements.
Solution Approach 2:
Each slit section has a locally optimized width: the first slit has a wider width for effective memory block isolation, while the second and third slits have different widths suited for their structural and transition functions. This local quality approach allows achieving reliable isolation without uniformly increasing precision requirements across the entire structure.
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a stack including interlayer sacrifice layers and interlayer insulation layers stacked alternatively. The stack includes a core region and a periphery region distributed along a first direction. The method also includes forming a gate line slit penetrating the stack and extending along the first direction. The gate line slit includes a first slit and a second slit interconnected with each other. The periphery region includes the first slit. The core region includes the second slit. The width of the first slit along the second direction is greater than the width of the second slit along the second direction. The second direction intersects with the first direction. The method further includes forming an isolation section in at least the first slit.