Semiconductor Gate Spacer Layout for Contact Protection and Vt Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in forming lower source/drain and gate contacts without damaging the gate pattern, controlling lateral growth of source/drain patterns, reducing parasitic capacitance, simplifying the cutting process of the gate pattern, and minimizing variation in threshold voltage (Vt).
Innovation Solution
A semiconductor device design that includes a gate inner spacer with overlapping and non-overlapping portions, a partition wall pattern, and self-alignment of contacts, which prevents gate pattern damage, controls lateral growth, reduces parasitic capacitance, and minimizes threshold voltage variation by protecting the work function metal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lower source/drain contact is formed using conventional methods, then the contact can be created, but the gate pattern may be damaged during the formation process
Solution Approach 1:
A placeholder pattern is introduced as an intermediary structure during the lower source/drain contact formation process. This placeholder serves as a protective mask that prevents the gate pattern from being damaged by etching or deposition processes, while still allowing the contact to be formed through it. After the contact is formed, the placeholder is removed. This mediator structure enables the contact formation without compromising gate integrity.
Solution Approach 2:
The placeholder pattern is formed in advance before the lower source/drain contact formation begins. This preliminary structure is strategically positioned to cover and protect the gate pattern areas that would be vulnerable during subsequent processing steps. By preparing this protective structure beforehand, the gate pattern is shielded from damage during the contact formation process.
2Ease of manufacture
If the gate pattern is extended to simplify the cutting process, then the cutting process is simplified, but parasitic capacitance increases due to recessed lower surface
Solution Approach 1:
The gate pattern is extended in the first direction (lateral extension) rather than extending in the third direction (vertical height). This dimensional change allows the gate to overlap with channel patterns laterally, simplifying the cutting process by eliminating the need for precise vertical alignment, while maintaining an elevated lower surface that prevents parasitic capacitance accumulation. The solution transitions from vertical extension to lateral extension to resolve the contradiction.
3Reliability
If additional structures like place holders are used to protect the gate pattern, then gate pattern damage is prevented, but device complexity increases
Solution Approach 1:
The placeholder pattern is designed as a temporary structure that is formed, used for protection during contact formation, and then completely removed after serving its purpose. This discarding approach means the placeholder does not remain in the final device structure, thus preventing permanent increase in device complexity while still providing necessary protection during manufacturing. The structure is recovered (removed) after fulfilling its protective function.
4Object-generated harmful factors
If the gate pattern is not extended, then parasitic capacitance is reduced, but the cutting process becomes more complex
Solution Approach 1:
The gate pattern extension is implemented in the first direction (lateral dimension) rather than the third direction (vertical dimension). This dimensional shift allows the gate to extend horizontally to overlap with channel patterns, which simplifies the cutting process by providing a larger margin for error and eliminating complex vertical alignment requirements, while simultaneously maintaining the lower surface elevation to prevent parasitic capacitance.
Data Source
AI summary
A semiconductor device includes active patterns spaced apart from one another in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern on the active patterns, in which the lower channel pattern and the lower source/drain pattern are alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer on the gate pattern, and between the lower source/drain pattern and the upper source/drain pattern.