Gate Stack Capping Structure for Multi-Vt Semiconductor Scaling
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) continue to scale down, challenges arise in maintaining functional density and geometry size, leading to issues such as increased complexity and reduced production efficiency.
Innovation Solution
The development of gate stacks for semiconductor devices, including high-k layers, work function layers, capping layers, and gate fill materials, is used to address the challenges of scaling down. These gate stacks are designed to improve the electrical properties of transistors, specifically by tuning the threshold voltage and enhancing the reliability of multi-gate devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase functional density, then production efficiency and cost are improved, but device complexity and manufacturing challenges increase
Solution Approach 1:
The gate structure is segmented into multiple distinct layers including high-k dielectric layer, work function layer, and capping layer. Each layer performs a specific function: the high-k dielectric provides gate insulation, the work function layer controls threshold voltage, and the capping layer protects underlying layers. This segmentation allows optimization of each layer independently while maintaining overall device performance at scaled dimensions.
Solution Approach 2:
The gate structure employs composite materials with different properties stacked together. The high-k dielectric material (e.g., HfO2, Al2O3) provides high breakdown voltage, the work function material (e.g., TiN, TaN) provides appropriate threshold voltage, and the capping material (e.g., SiN, SiO2) provides protection. This composite approach enables the device to achieve desired electrical characteristics at smaller geometries without excessive complexity in any single material system.
2Reliability
If gate stack structures are implemented to improve electrical properties and reliability, then device performance is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The gate structure is formed with preliminary actions taken during fabrication: the high-k dielectric layer is deposited first to establish the gate insulation foundation, followed by the work function layer to pre-establish threshold voltage characteristics, and finally the capping layer to pre-protect the structure. This sequential preliminary action approach ensures each layer is optimized before the next is added, improving reliability while managing process complexity through a structured fabrication flow.
Solution Approach 2:
Different regions of the gate structure have different material compositions and properties tailored to local requirements. The high-k dielectric layer has high permittivity for gate insulation, the work function layer has specific work function values for threshold control, and the capping layer has protective properties. This local quality differentiation ensures each part of the gate stack performs its specific function optimally, enhancing overall device reliability.
Data Source
AI summary
A semiconductor device includes a substrate, a first gate structure, and a second gate structure. The first gate structure is disposed on the substrate. The first gate structure includes a first capping layer and a first underlying layer below the first capping layer. The second gate structure is disposed on the substrate. The second gate structure includes a second capping layer and a second underlying layer below the second capping layer. The material of the first capping layer and the second capping layer have a material having higher resistant to oxygen or fluorine than materials of the first underlying layer and the second underlying layer. The first capping layer, the second capping layer and the second underlying layer include a same metal element.