Gate Electrode Extension Into STI for Lower LDMOS RDS(on)
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
LDMOS transistors face challenges in reducing drain-source on resistance (RDS(on)) which affects switching speeds and reliability, due to factors like channel region area and substrate resistance, and the introduction of a shallow trench isolation (STI) structure increases channel path length, thereby increasing RDS(on).
Innovation Solution
A bowl-shape portion of the gate electrode is extended into the STI structure, increasing the accumulation area of mobile charge carriers below the STI structure, reducing RDS(on) without altering the transistor's dimensions, thereby improving switching speeds and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a shallow trench isolation (STI) structure is introduced to improve device isolation and breakdown voltage, then device reliability is improved, but the channel path length increases, thereby increasing drain-source on resistance (RDS(on))
Solution Approach 1:
The gate electrode is extended vertically into the STI structure along the depth dimension, creating a multi-level gate configuration. This vertical extension allows the gate to control charge carriers in the drift region without increasing the lateral channel length, thereby reducing RDS(on) while maintaining the STI structure's reliability benefits
Solution Approach 2:
The gate electrode configuration is made non-uniform by extending it selectively into the STI structure only in regions where additional charge carrier control is needed. This local modification allows precise control of the electric field distribution in the drift region without affecting the entire device structure
2Area of stationary object
If the channel region area is reduced to improve device integration density, then device size is reduced, but switching speed and current capability deteriorate
Solution Approach 1:
The invention transitions from a two-dimensional gate control to a three-dimensional configuration by extending the gate vertically into the STI structure. This allows effective gate control volume to increase without increasing the device footprint, maintaining switching speed while improving integration density
3Speed
If substrate resistance is reduced to improve switching speed, then switching speed is improved, but device complexity increases due to additional doping regions and process steps
Solution Approach 1:
The extended gate electrode structure serves multiple functions simultaneously: it controls the channel, modulates the drift region electric field, and reduces on-resistance without requiring additional doping regions or complex process steps. The single structural modification achieves what would otherwise require multiple separate components
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.