Gate Unit Electrochemical Deposition for Fast Charging

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing methods for manufacturing array substrates used in TFT-type display screens result in long charging times, which do not meet current demands for high performance and efficiency.

Innovation Solution

A method involving the electrochemical deposition of a functional material on a photoresist layer with a pattern to form a conductive layer with a pattern layer, which is then used to create a gate unit for the array substrate, allowing for shorter charging times and improved conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional etching method is used to form pattern on conductive layer, then manufacturing process is simple, but charging time is long

Engineering Contradiction:

Improvecharging timeVSAvoidmanufacturing process complexity

Core Design Contradiction:

Loss of timeVSEase of manufacture

Solution Approach 1:

The patent replaces the conventional mechanical/chemical etching process with an electrochemical deposition process. Instead of removing material through etching, the invention deposits a functional material layer through electrochemical reactions, fundamentally changing the manufacturing approach to achieve both shorter charging times and feasible manufacturing.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the manufacturing parameters by introducing electrochemical deposition with specific control of deposition potential, current density, and electrolyte composition. These parameter changes enable precise control over the functional material layer properties, achieving high conductivity patterns that reduce charging time while maintaining manufacturability.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If electrochemical deposition is used to form pattern layer, then conductivity is improved, but process complexity increases

Engineering Contradiction:

ImproveconductivityVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a photoresist layer as an intermediary that defines the pattern geometry before electrochemical deposition. This intermediary enables precise spatial control of the functional material deposition, ensuring high conductivity patterns are formed only where needed, thereby achieving improved conductivity without excessive overall process complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent performs preliminary actions by first forming the photoresist pattern layer before conducting electrochemical deposition. This preliminary patterning step prepares the substrate in advance, guiding where the functional material will be deposited and ensuring optimal conductivity patterns are achieved with controlled process complexity.

Inventive Principle:

Principle #10Preliminary action

3Loss of time

If pattern layer with higher density is obtained, then charging time is reduced, but manufacturing precision requirements increase

Engineering Contradiction:

Improvepixel charging timeVSAvoiddeposition precision

Core Design Contradiction:

Loss of timeVSManufacturing precision

Solution Approach 1:

The patent employs feedback control in the electrochemical deposition process by monitoring and adjusting deposition potential and current density. This feedback mechanism ensures precise control over the functional material layer formation, achieving high-density patterns that reduce charging time while maintaining manufacturing precision through real-time process adjustment.

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves a conductivity range of 3.0*10^6 S/m to 8.0*10^6 S/m for the gate unit, reducing pixel charging time to 10 μs to 15 μs and enhancing the refresh rate of the array substrate.

Implementation Method 1

exposing the photoresist layer, and then developing the photoresist layer to form a groove extending through the photoresist layer on the photoresist layer

Methodology Applied

Scientific EffectPhotochemical reaction: Photopolymerisation

Implementation Method 2

electrochemically depositing a functional material on the photoresist layer with the pattern

Methodology Applied

Scientific EffectElectrochemical deposition: Electrodeposition

Implementation Method 3

electrifying the electrolyte under a first reduction potential or a first reduction current, so that the first ions are reduced and deposited on the photoresist layer with the pattern to form a metal material layer

Methodology Applied

Scientific EffectElectrochemical reduction: Redox Reactions

Data Source

PatentUS11515342B2Gate unit and manufacturing method thereof, array substrate manufacturing method, and display mechanism

Publication Date: 2022.11.29 BEIHAI HKC OPTOELECTRONICS TECH CO LTD

AI summary

A gate unit and a manufacturing method thereof, a method of manufacturing an array substrate, and a display mechanism are provided. The method of manufacturing a gate unit includes: providing a conductive layer on a substrate; forming a photoresist layer on a side of the conductive layer away from the substrate; exposing the photoresist layer, and then developing the photoresist layer to form a groove extending through the photoresist layer on the photoresist layer, so as to form the photoresist layer with a pattern; and electrochemically depositing a functional material on the photoresist layer with the pattern, and then removing the photoresist layer to obtain the conductive layer having a pattern layer formed thereon, so as to obtain the gate unit.