Mirror-Symmetric Gate Via Layout for Lower MOS Gate Resistance
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Solution Overview
Problem
As semiconductor technology nodes shrink, the gate resistance in MOS transistors increases, leading to elevated RC delay, which hampers the performance of smaller and more functional electronic devices.
Innovation Solution
The integrated circuit structure incorporates two transistors with conductive vias electrically connecting the gate electrodes to a connection line, reducing gate resistance and RC delay by structurally separating the gate electrodes and optimizing the placement of conductive vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are reduced to increase device density, then more transistors can be packed into smaller devices, but gate resistance increases leading to elevated RC delay
Solution Approach 1:
The gate electrode is divided into multiple segments with conductive vias inserted between them, creating a segmented gate structure. This segmentation reduces the effective gate resistance by providing multiple parallel conduction paths while maintaining the overall gate functionality, thereby resolving the RC delay issue that arises from scaling down transistor dimensions.
Solution Approach 2:
The conductive via extends the gate electrode connection into the vertical dimension, creating a three-dimensional gate structure. This additional dimensional approach allows for reduced gate resistance by providing vertical conduction paths through the via, effectively addressing the RC delay problem without further reducing the already minimized horizontal transistor dimensions.
2Length of moving object
If gate electrode dimensions are reduced to match smaller transistor nodes, then transistor scaling is achieved, but gate resistance increases
Solution Approach 1:
The gate electrode is segmented into multiple sections separated by conductive vias, transforming a single long resistive path into multiple shorter parallel paths. This segmentation directly addresses the increased gate resistance caused by reduced gate electrode length in scaled transistors.
Solution Approach 2:
The conductive via acts as an intermediary element that connects different segments of the gate electrode. This intermediary structure provides additional conduction pathways and reduces the overall gate resistance, compensating for the effects of reduced gate electrode dimensions in scaled transistors.
3Ease of manufacture
If conventional transistor structures are used in smaller nodes, then manufacturing simplicity is maintained, but performance degrades due to high RC delay
Solution Approach 1:
The gate electrode is divided into segments with conductive vias, creating a structured modification that can be integrated into conventional manufacturing processes. This segmentation approach maintains ease of manufacture by using standard fabrication techniques while significantly improving performance by reducing RC delay.
Solution Approach 2:
The gate electrode structure is modified by changing its physical parameters - specifically by adding vertical via connections and segmenting the horizontal path. This parameter change transforms the electrical characteristics to reduce resistance without fundamentally altering the manufacturing process complexity, thereby improving RC delay while maintaining ease of manufacture.
Data Source
AI summary
An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.