Gate Driving Voltage Line Layout for Stable OLED Node Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing organic light emitting display devices face issues with fluctuations in the critical node voltage of the gate driving circuit, leading to deteriorated performance and sensing characteristics.
Innovation Solution
A display device and panel design that includes a gate driving circuit with multiple gate high-potential voltage lines to stabilize the critical node voltage, minimizing fluctuations and maintaining stable operation at low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate driving circuit is used with single voltage lines, then the device complexity is low, but the critical node voltage fluctuates and performance deteriorates
Solution Approach 1:
The gate high-potential voltage line is segmented into multiple separate voltage lines (first gate high-potential voltage line and second gate high-potential voltage line) that are branched from different power supply nodes. This segmentation allows independent voltage stabilization for different nodes (Q node and QB node), preventing voltage fluctuations from affecting the entire gate driving circuit simultaneously and thereby improving critical node voltage stability.
2Reliability
If multiple voltage lines are used to stabilize critical node voltage, then voltage stability improves, but the device complexity increases
Solution Approach 1:
Different gate high-potential voltage lines are provided for different local nodes (Q node and QB node) within the gate driving circuit. Each voltage line is specifically designed to stabilize the voltage at its corresponding node, applying local quality improvement rather than uniform stabilization throughout the entire circuit. This approach targets voltage stability where it is most needed while minimizing unnecessary complexity in other areas.
Data Source
AI summary
A display panel comprising a display area including a plurality of subpixels, a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, and a plurality of gate high-potential voltage lines which are disposed in the non-display area for transferring a plurality of gate high-potential voltages to the gate driving circuit, wherein plurality of gate high-potential voltage lines include a first gate high-potential voltage line transferring a first gate high-potential voltage for charging a first node of the gate driving circuit, a second gate high-potential voltage line transferring a second gate high-potential voltage for charging a second node of the gate driving circuit, and a third gate high-potential voltage line which is branched from the first gate high-potential voltage line for transferring a third gate high-potential voltage to stabilize a transistor controlling the first node.