Gate Wiring Loop Reduces Common Source Inductance
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Solution Overview
Problem
Common source inductance in discrete semiconductor power switching devices, particularly in inverter drive systems for electrified vehicles, limits switching speed and increases switching losses due to parasitic inductance associated with packaging and printed circuit board traces, which is exacerbated by the faster switching times of new power device generations.
Innovation Solution
The introduction of a gate wiring loop juxtaposed with the power signal path on a circuit board, creating a negative mutual inductance that cancels the inherent positive mutual inductance, thereby reducing common source inductance and minimizing switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If discrete power switching devices are packaged in traditional TO packages and mounted on PCB with conventional trace layouts, then device packaging and mounting are simplified, but common source inductance increases to as high as 10 nH, limiting switching speed and increasing switching losses
Solution Approach 1:
The patent transitions from planar PCB trace layouts to a three-dimensional wirebond configuration. The gate wiring loop is formed by wirebonds connecting the gate pin to the source pin through a vertical loop structure, utilizing the third dimension (vertical space above the device) to create a compact loop that closely couples with the power signal path, thereby reducing common source inductance while maintaining ease of manufacture
2Speed
If new generations of power devices (CoolMOS, SiC, GaN) with faster switching capabilities are used, then switching speed capability is improved, but the common source inductance from conventional packaging becomes more significant, dramatically limiting the achievable switching speed
Solution Approach 1:
The patent applies local quality by creating a specialized gate wiring loop configuration specifically at the critical gate drive connection point. The wirebond loop is positioned to closely follow the power signal path locally, providing optimized magnetic coupling only where needed (at the source pin connection), rather than requiring complete redesign of the entire device or PCB layout
3Ease of operation
If conventional PCB trace routing is used for gate signals, then routing simplicity is maintained, but the mutual inductance between gate and power traces creates voltage interference that limits switching performance
Solution Approach 1:
The patent converts the harmful mutual inductance effect into a beneficial one by deliberately designing the gate wiring loop to have controlled negative mutual inductance with the power signal path. The wirebond loop configuration creates opposing magnetic flux that actively cancels the parasitic inductance, transforming the interference problem into a solution that reduces common source inductance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces common source inductance, thereby enhancing switching speed and reducing switching losses by more than 50%, improving the efficiency of discrete power switching devices in inverter drive systems.
Implementation Method 1
A circuit board apparatus provides a gate wiring loop juxtaposed with the power signal path, wherein the gate wiring loop and the power signal path have a second mutual inductance substantially canceling the first mutual inductance
Data Source
AI summary
Routing of a gate signal for controlling a discrete power switching device (such as in an inverter for an electric vehicle drive) is configured to compensate for the common source inductance inherent in the switching device as a result of its integrated circuit packaging. The power device has a gate signal path via a gate pin and a power signal path via first and second power pins, wherein the gate signal path and the power signal path have a first mutual inductance. A circuit board apparatus provides a gate wiring loop juxtaposed with the power signal path, wherein the gate wiring loop and the power signal path have a second mutual inductance substantially canceling the first mutual inductance. The resulting reduction in common source inductance avoids the reductions in switching speed and the increased switching losses otherwise introduced by the common source inductance.