Semiconductor Module Gate Wiring Geometry for Uniform Gate Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor modules with multiple semiconductor elements experience undesired variations in gate voltage due to varying lengths of conductive paths from signal terminals to gate electrodes, leading to delays in switching operations.
Innovation Solution
The semiconductor device configuration includes two semiconductor elements with specific electrode and gate electrode arrangements, where a sealing resin covers the elements and a signal wiring connects the gate electrodes to a signal terminal, ensuring uniform gate voltage application by optimizing the path lengths and cross-sectional areas of the signal wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single signal terminal is used to connect multiple semiconductor elements, then the device complexity is reduced, but the gate voltage uniformity deteriorates due to varying conductive path lengths
Solution Approach 1:
The patent applies local quality by making the signal wiring cross-sectional area vary along its length. The wiring has a larger cross-sectional area at sections with longer current paths and smaller cross-sectional area at sections with shorter current paths. This local variation in wiring geometry compensates for the varying path lengths from different semiconductor elements to the signal terminal, ensuring uniform gate voltage application while maintaining a simple single-terminal configuration.
2Speed
If the conductive path length from signal terminal to gate electrode is reduced, then the switching speed is improved, but the gate voltage uniformity across multiple semiconductor elements deteriorates
Solution Approach 1:
The patent changes the geometric parameters of the signal wiring, specifically varying its cross-sectional area along the length of the wiring. By adjusting the wiring cross-section to be larger where current paths are longer and smaller where paths are shorter, the patent optimizes both the switching speed (by keeping overall path lengths short) and gate voltage uniformity (by compensating for path length differences through cross-sectional variations).
Data Source
AI summary
A semiconductor device includes a first semiconductor element with a first gate electrode, a second semiconductor element with a second gate electrode, a sealing resin, a first signal terminal with a third center, and a first signal wiring. The first line connecting the first center of the first gate electrode and the third center has a first line length L1. The second line connecting the second center of the second gate electrode and the third center has a second line length L2. The path from the first center to the third center via the first signal wiring has a first path length R1. The path from the second center to the third center via the first signal wiring has a second path length R2. In the semiconductor device, R2/R1 is closer to 1 than is L2/L1.