Gate-Wrap-Around Transistor Fabrication with Internal Spacers
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Solution Overview
Problem
Existing processes for fabricating gate-wrap-around field-effect transistors fail to maintain significant prestrain in the channels of pMOS and nMOS transistors, leading to degraded performance, particularly due to the relaxation of silicon channels and inadequate strain in the channel zone during the formation of source and drain by epitaxy.
Innovation Solution
A process that forms internal spacers extending from the source to the drain zone while preserving nanowires, allowing for the maintenance of high prestrain in the channel zones, specifically using ion implantation and selective etching to create voids and fill them with dielectric material, which helps in maintaining tensile prestrain in nMOS and compressive prestrain in pMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source and drain are formed by epitaxy, then the fabrication process is simplified, but the desired strain cannot be obtained in the channel zone of silicon nanowires
Solution Approach 1:
The patent applies preliminary action by forming internal spacers in cavities before the epitaxial growth of source and drain. These pre-formed spacers serve as strain-preserving structures that maintain the desired tensile or compressive strain in the channel zone during subsequent processing steps, including epitaxy. The spacers are positioned to physically constrain the nanowire channel, preventing relaxation of strain that would otherwise occur during source/drain formation.
2Reliability
If silicon nanowires are initially tensilely strained, then nMOS transistor performance is improved, but the strain relaxes during fabrication leading to degraded performance
Solution Approach 1:
The patent introduces internal spacers as intermediary structures that mediate between the silicon nanowire channel and the surrounding environment. These spacers act as mechanical constraints that maintain the tensile strain in silicon nanowires for nMOS transistors throughout the fabrication process. The spacers are formed in cavities surrounding the nanowires and provide continuous physical support that prevents strain relaxation, thereby preserving the improved carrier mobility and transistor performance.
3Reliability
If SiGe nanowires are initially compressively strained, then pMOS transistor performance is improved, but the strain relaxes during fabrication leading to degraded performance
Solution Approach 1:
The patent uses internal spacers as intermediary structures to maintain compressive strain in SiGe nanowires for pMOS transistors. The spacers are formed in cavities surrounding the SiGe nanowires and provide mechanical constraint that prevents relaxation of the compressive strain during fabrication. This intermediary structure ensures that the beneficial effects of compressive strain on hole mobility and pMOS transistor performance are preserved throughout the manufacturing process.
4Ease of manufacture
If internal spacers are formed by removing sacrificial material, then the process is simplified, but strain may be lost during material removal
Solution Approach 1:
The patent employs sacrificial material as a temporary intermediary structure that facilitates the formation of internal spacers without directly contacting or damaging the nanowire channel. The sacrificial material is deposited, patterned, and etched to define the spacer geometry, then selectively removed to create cavities. The internal spacers are subsequently formed in these cavities. This intermediary approach allows complex spacer structures to be created while protecting the nanowire strain from damage during the formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively maintains significant prestrain in the channel zones of gate-wrap-around transistors, enhancing the electrical performance by preserving the tensile strain in silicon nanowires and compressive strain in SiGe nanowires, thereby improving the overall performance of both pMOS and nMOS transistors.
Implementation Method 1
A process is provided wherein internal spacers are formed in cavities which are formed in a nanowire stack
Implementation Method 2
The portion of the silicon-germanium nanowires under the spacers is removed by selective etching, so as to form cavities under these spacers
Implementation Method 3
Internal spacers are then deposited in the interior of the cavities
Implementation Method 4
In a step of growing silicon-germanium epitaxially, a source and a drain are formed on either side of the stack
Data Source
AI summary
A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.