Gate Zero Template for Sub-50nm Semiconductor Spacing
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Solution Overview
Problem
The miniaturization of semiconductor devices poses challenges in achieving gate spacings of less than 50 nm or 30 nm, particularly for devices using quantum effects, as existing methods are complex, prone to errors, and introduce charge noise due to extra dielectrics or tip shrinkage during etching.
Innovation Solution
A method involving a 'gate zero' layer as a self-aligned mask for a 'gate one' layer, using negative tone resist electron beam lithography to form a template structure with sub-structures less than the critical dimension, allowing precise patterning and selective removal to achieve small spacings between gates, thereby simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If overlapping multiple gate layers is used to achieve small gate spacing, then gate spacing can be reduced, but device complexity increases and charge noise is introduced due to extra gate dielectrics
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming a template structure with sub-structures, depositing gate material, selectively removing gate material over template regions, and finally removing the template structure. This segmentation allows achieving small gate spacing without stacking multiple gate layers, thus reducing device complexity and eliminating charge noise from extra dielectrics
Solution Approach 2:
A template structure is formed in advance before gate deposition. This template structure with predetermined sub-structures serves as a guide for subsequent gate patterning, enabling precise gate spacing control without requiring complex multi-layer alignment processes
2Length of stationary object
If cut lithography with etching is used to form separate gates, then gate spacing can be controlled, but tip shrinkage of 15-20 nm occurs during etching making sub-50 nm spacing难以实现
Solution Approach 1:
The template structure with precisely defined sub-structures is formed before gate material deposition. This preliminary structuring establishes the exact gate spacing and dimensions without relying on subsequent etching processes that would cause tip shrinkage
Solution Approach 2:
The template structure acts as an intermediary element that transfers the desired gate pattern to the gate material during deposition. This intermediary approach avoids direct etching of gate tips, eliminating the 15-20 nm tip shrinkage problem associated with conventional cut lithography
3Length of stationary object
If a thick spacer is grown underneath one gate in a spacer-defined process, then gate spacing can be defined, but it becomes difficult to pattern the two vertically displaced gates and remove the spacer
Solution Approach 1:
The process separates template structure formation from gate structure formation. The template structure with sub-structures is formed first, then gate material is deposited and selectively removed, and finally the template structure is removed. This segmentation eliminates the difficulty of patterning vertically displaced gates and removing spacers
Solution Approach 2:
The template structure serves as a temporary intermediary that defines gate positions during fabrication. Unlike permanent spacers that create vertical displacement, this template approach maintains coplanarity and simplifies both patterning and removal steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reliably achieves gate spacings of less than 50 nm or 30 nm, improving spin-qubit readout sensitivity while reducing charge noise and process complexity, suitable for devices like single electron transistors and quantum dots.
Implementation Method 1
using a 'gate zero' (G0) layer that acts as a self-aligned mask for a 'gate one' (G1) layer
Implementation Method 2
using negative tone resist electron beam lithography to form a template structure with sub-structures less than the critical dimension
Implementation Method 3
removing the part of the gate layer formed on the template structure; selectively removing the template structure
Data Source
AI summary
A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.