Gated Clock Circuit for Accurate PDN Impedance Measurement
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Solution Overview
Problem
Existing power delivery networks face challenges in efficiently measuring impedance due to the large on-chip area occupied by current sinks, which can also induce leakage currents.
Innovation Solution
A system comprising a signal generating device, a processing device, and a measuring device, where the signal generating device generates a gated clock signal to adjust the voltage difference measured by the measuring device, ensuring alignment of edges in the enable signal and clock signal to minimize jitter and improve impedance measurement accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a current sink is used to measure impedance in the power delivery network, then the impedance measurement can be performed, but the current sink occupies large on-chip area and induces leakage current
Solution Approach 1:
The patent extracts the impedance measurement function from the traditional current sink architecture and implements it using a capacitor-based voltage modulation approach. The measuring device applies a voltage signal to the power delivery network and measures the resulting current by detecting voltage changes across a known capacitor, eliminating the need for a large current sink circuit on the chip.
Solution Approach 2:
The patent changes the measurement parameter from direct current measurement (requiring current sink) to voltage measurement across a capacitor. By measuring voltage changes ΔV during charging/discharging cycles of a capacitor with known capacitance C, the current can be indirectly determined using I = C·dV/dt, thereby avoiding the area and leakage issues of current sinks.
2Measurement precision
If a current sink is used to measure impedance in the power delivery network, then the impedance measurement can be performed, but leakage current is induced
Solution Approach 1:
The patent removes the current sink component that generates leakage current and replaces it with a capacitor-based voltage measurement system. The measuring device charges and discharges a capacitor through the power delivery network and measures voltage transitions, indirectly determining impedance without the harmful leakage effects of current sinks.
Solution Approach 2:
The patent uses a capacitor that is periodically charged and discharged for measurement purposes only. The capacitor serves its function during brief measurement intervals and then resets, avoiding the continuous operation and associated leakage currents of a traditional current sink while maintaining measurement accuracy.
3Productivity
If jitter is not minimized in the gated clock signal, then the impedance measurement can be performed, but the measurement accuracy deteriorates
Solution Approach 1:
The patent employs a feedback mechanism where the measuring device monitors the actual voltage transitions and adjusts the gating signal timing accordingly. The controller synchronizes the sampling moments with the voltage edges, and any timing deviations (jitter) are compensated through feedback control, ensuring accurate impedance measurement even in the presence of clock variations.
Solution Approach 2:
The patent performs preliminary synchronization of the gating clock signal with the voltage transitions before actual measurement begins. The system pre-aligns the sampling moments with expected voltage edges and establishes proper timing relationships, thereby minimizing the impact of subsequent jitter during the actual impedance measurement process.
Data Source
AI summary
A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.