Gated SCR Structure for ESD Trigger and Holding Voltage Control
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Solution Overview
Problem
Integrated circuits are vulnerable to damage from random electrostatic discharge (ESD) events due to the limitations of existing silicon-controlled rectifier (SCR) devices in effectively managing ESD currents, particularly in their triggering and holding voltage thresholds.
Innovation Solution
A device structure comprising a semiconductor substrate with specifically doped regions and wells, along with a gate structure, is designed to enhance the SCR's performance by modifying the triggering and holding voltages, and including a floating doped region segmented into sections to improve on-resistance and failure current, integrating an insulated gate bipolar transistor for efficient ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SCR devices are used for ESD protection, then the device structure is simple, but the triggering and holding voltage thresholds are inadequate for effective ESD current management
Solution Approach 1:
The SCR device is segmented into multiple doped regions (first doped region, second doped region, third doped region with first and second portions) and wells (first well, second well) with different conductivity types. This segmentation allows independent optimization of triggering and holding voltage thresholds while maintaining overall device functionality for ESD protection.
Solution Approach 2:
Different regions of the device are assigned different doping concentrations and conductivity types to create localized electrical characteristics. The first doped region has one conductivity type while the second doped region has the opposite conductivity type, enabling precise control of voltage thresholds in specific areas to improve ESD protection effectiveness.
2Reliability
If the SCR device is designed with higher triggering voltage threshold, then ESD current management improves, but the device area increases
Solution Approach 1:
The patent utilizes vertical dimension by forming doped regions at different depths in the semiconductor substrate through multiple wells (first well, second well) and layered doped regions. This three-dimensional structure allows achieving higher voltage thresholds without proportionally increasing the lateral device area, as the electrical characteristics are controlled through vertical doping profiles rather than lateral expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved area-efficient medium- and high-voltage electrostatic discharge protection, effectively shielding integrated circuits from ESD events without requiring additional processing masks, thereby enhancing the reliability and efficiency of ESD protection.
Implementation Method 1
In its quiescent high-impedance state, the SCR restricts current conduction to leakage current
Implementation Method 2
a gate structure that overlaps with a portion of the second well
Data Source
AI summary
Device structures including a silicon-controlled rectifier and methods of forming a device structure including a silicon-controlled rectifier. The device structure comprises a first well and a second well in a semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite from the first conductivity type. The second well adjoins the first well along an interface. A third doped region includes a first portion in the first well and a second portion in the second well, and a gate structure that overlaps with a portion of the second well.