Thyristor TRIZ Cases
- SiC Transistor Cell Clamp Structure for Gate Overvoltage Protection
A bidirectional clamp in a SiC transistor cell creates low-resistive gate-source paths to dissipate overvoltage and ESD while limiting leakage.
- IGBT ESD Protection Structure With Low Capacitance and No Snapback
An antiparallel-diode IGBT structure lowers ESD trigger voltage and capacitance while avoiding snapback in data transmission circuits.
- SCR ESD Protection Circuit for Lower Trigger and Latch-Up Resistance
A P-type floating region and non-sal layer tune SCR holding and trigger voltages to improve ESD current handling and resist latch-up.
- SCR Clamp Circuit Layout for Low-Voltage ESD Protection
Gate-triggered SCR clamp circuits lower ESD trigger voltage while maintaining hold voltage, protecting low-voltage internal circuits with minimal area.
- Trench MOSFET Sidewall Structure for Lower On-Resistance
Inclined trench sidewalls and segmented doped regions improve electron mobility, lower on-resistance, and support higher current handling.
- Avalanche Diode Well Structure for Stable High-Voltage Clamping
A thin field relief oxide over spaced shallow wells moves the high-field region away from trapped-charge interfaces for steadier breakdown.
- Porous SCR Well Junctions for Lower Trigger Voltage and Smaller Footprint
Adding a porous region between adjacent SCR wells lowers trigger voltage, improves holding current, and preserves a compact footprint.
- Thyristor Memory Cell Structure for Capacitor-Less DRAM Scaling
Using thyristor conduction and blocking states, this case shows how capacitor-less memory cells support DRAM scaling without losing signal identification.
- Thyristor Drift Region Doping for Lower On-State Voltage
A doped tub structure locally thins the thyristor drift region to cut peak on-state voltage while preserving reverse-bias blocking capability.