IGBT ESD Protection Structure With Low Capacitance and No Snapback
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Solution Overview
Problem
Existing data transmission systems face challenges with electrostatic discharge (ESD) protection due to high trigger voltages and capacitance issues, which can lead to component damage during ESD events, and current solutions like semiconductor controlled rectifiers (SCRs) have limitations in reducing trigger voltage and capacitance effectively.
Innovation Solution
An insulated-gate bipolar transistor (IGBT) device with a specific doping structure and antiparallel diode configuration is proposed, which includes regions doped with different types of charge carriers, a gate structure, and diode structures to function as a stand-alone ESD protection device or trigger, reducing capacitance and avoiding voltage snapback, allowing for higher current density and low ohmic contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a MOSFET is used for ESD protection, then the device structure is simple, but the capacitance is very high due to its size and gate oxide
Solution Approach 1:
The device is segmented into a MOSFET structure and an integrated bipolar transistor structure, allowing the MOSFET to provide simple device control while the bipolar structure provides low capacitance for ESD protection, thus resolving the contradiction between structural simplicity and low capacitance requirements
2Reliability
If the Gate terminal is connected to one of the terminals in a two-pin ESD protection device, then the device can function as ESD protection, but the capacitance increases further due to the thin gate oxide
Solution Approach 1:
The gate terminal is extracted from the traditional two-pin configuration and integrated into the bipolar transistor structure as a control element rather than a separate terminal, allowing the ESD protection function to be maintained while eliminating the parasitic capacitance associated with a separate gate terminal connection
3Quantity of substance
If open base transistors are used to reduce capacitance, then the capacitance can be tuned to low values, but the device exhibits snapback which may not be desirable
Solution Approach 1:
The MOSFET acts as an intermediary between the control signal and the bipolar transistor, providing stable voltage control through its threshold voltage characteristic while the bipolar transistor provides low capacitance, thus eliminating the unwanted snapback effect while maintaining low capacitance and voltage stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The IGBT device achieves low trigger voltage, reduced capacitance, and higher current density, effectively protecting against ESD events while minimizing parasitic capacitance, thus enhancing the reliability of data transmission systems.
Implementation Method 1
The low capacitance of the pair of antiparallel diode devices hides the high capacitance of the gate oxide of the gate structure
Implementation Method 2
a first region doped with a first type of charge carriers; a second region doped with a second type of charge carriers different from the first type of charge carriers; a third region doped with the first type of charge carriers; a fourth region doped with the second type of charge carriers
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
An insulated-gate bipolar transistor device comprising: a first region doped with a first type of charge carriers; a second region doped with a second type of charge carriers different from the first type of charge carriers; a third region doped with the first type of charge carriers; a fourth region doped with the second type of charge carriers; a first, emitter terminal electrically connected with the first region and a second, collector terminal electrically connected with the third region and the fourth region; and a gate structure disposed on the third region with one end adjacent to the second region and with another end adjacent the fourth region; as well as a diode structure having a first diode structure terminal electrically connected with the collector terminal and a second diode structure terminal electrically connected with the gate terminal of the gate structure, wherein the diode structure is a paired antiparallel diode structure with a total capacitance no greater than 200 femto-Farads.