Thyristor Memory Cell Structure for Capacitor-Less DRAM Scaling
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Solution Overview
Problem
As DRAM cell sizes decrease, securing sufficient cell capacitance to identify stored signals becomes increasingly difficult, prompting research into capacitor-less 1T DRAM devices, with thyristor memory devices being proposed as a solution.
Innovation Solution
A semiconductor device incorporating memory cells with a thyristor structure, featuring pillar electrodes, shared device layers, base device layers, and a control gate electrode, utilizing p-type and n-type metal oxide semiconductor materials to achieve electrical conduction and blocking states for signal storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM cell size is decreased to increase storage density, then storage capacity is improved, but cell capacitance becomes insufficient for reliable signal identification
Solution Approach 1:
The patent changes the fundamental parameter of memory storage from capacitance-based (voltage level) to resistance-based (conduction state). By using the thyristor's bistable resistance states (high and low resistance) to represent binary data, the invention eliminates the need for large capacitor structures, enabling high-density storage while maintaining reliable signal identification through resistance measurement.
Solution Approach 2:
The patent substitutes the electrical capacitance mechanism with a resistive switching mechanism. Instead of storing data as electrical charge in a capacitor, the invention stores data as the conduction state (resistance level) of the thyristor, which is determined by the configuration of metal oxide semiconductor layers with different resistance states.
2Reliability
If conventional 1T-1C structure is used, then signal storage is achieved, but device complexity increases and scaling becomes difficult
Solution Approach 1:
The patent extracts and removes the capacitor component from the conventional 1T-1C memory structure. By using the thyristor's inherent bistable resistance states to store data, the invention eliminates the need for a separate capacitor, reducing device complexity from two components (transistor + capacitor) to a simpler structure while maintaining signal storage capability.
Solution Approach 2:
The patent makes the thyristor perform multiple functions: it acts as both the storage element (replacing the capacitor) and the switching element. The thyristor's ability to maintain stable resistance states enables it to function as a non-volatile memory element, while its transistor-like behavior allows for controlled switching, consolidating multiple functions into a single device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient storage and retrieval of signal information by controlling the electrical conduction and blocking states of thyristors, effectively addressing the challenge of reducing cell size while maintaining signal identification capabilities.
Implementation Method 1
an electrical conduction state and an electrical blocking state implemented using turn-on and turn-off operations of the thyristor may be stored as different signal information
Implementation Method 2
a first shared device layer including a p-type metal oxide semiconductor material and extending along the vertical direction, a first base device layer disposed over the substrate to contact the first shared device layer
Data Source
AI summary
A semiconductor device according to an embodiment includes a substrate, first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate, and a plurality of memory cells disposed between the first and second pillar electrodes. Each of the plurality of memory cells includes first and second shared device layers that are disposed adjacent to the first and second pillar electrodes, respectively, and extend along the vertical direction, first and second base device layers disposed between the first and second shared device layers, and a control gate electrode disposed on one of the first and second base device layers. Both first and second base device layers are disposed on a plane over the substrate and substantially parallel to the surface of the substrate.