Graph Convolutional Network for Netlist Test Point Insertion

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Solution Overview

Problem

Deep learning techniques face challenges in applying to Computer Aided Design (CAD) and Electronic Design Automation (EDA) problems, particularly in representing netlists as directed acyclic graphs, where preprocessing requires human expert considerations and results in data loss, making it difficult to identify difficult-to-test nodes.

Innovation Solution

A pre-processor is developed to levelize netlists, compute controllability and observability metrics, and apply a SCOAP algorithm to encode netlist connectivity, followed by a graph convolutional network (GCN) to predict difficult-to-test nodes and insert test points for improved testability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If netlists are preprocessed using traditional methods, then data structure is preserved for processing, but data loss occurs and human expert consideration is required

Engineering Contradiction:
Improvedata lossVSAvoidpreprocessing complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent replaces traditional mechanical preprocessing methods with a graph convolutional network (GCN) based deep learning approach. The GCN automatically learns to preserve essential netlist characteristics while transforming the data into a format suitable for processing, eliminating manual expert intervention and reducing information loss through automated feature extraction and preservation mechanisms.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If deep learning techniques are applied to netlists, then processing speed is improved, but difficulty in representing netlists as DAGs increases

Engineering Contradiction:
Improveprocessing speedVSAvoidrepresentation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the netlist representation into a directed acyclic graph (DAG) structure where nodes represent logic blocks and edges represent connections. This segmentation transforms the complex netlist data into a hierarchical structure that deep learning models can process efficiently, maintaining processing speed while managing representation complexity through structured decomposition.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a graph convolutional network as an intermediary between the netlist input and the deep learning processing pipeline. The GCN serves as a mediator that automatically handles the transformation and representation of netlists as DAGs, reducing the complexity burden on subsequent processing stages while maintaining high processing speed through optimized graph-based operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If test points are inserted to improve testability, then observability and controllability are improved, but circuit complexity increases

Engineering Contradiction:
ImprovetestabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies partial action by selectively inserting test points only at critical locations identified by the deep learning model, rather than uniformly across the entire circuit. The GCN analyzes the netlist and identifies specific nodes where test point insertion will maximally improve observability and controllability, thereby enhancing testability while minimizing the increase in circuit complexity through targeted rather than comprehensive test point placement.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11574097B2Deep learning based identification of difficult to test nodes
Publication Date: 2023.02.07 NVIDIA CORP
  • US11574097B2 patent drawing
  • US11574097B2 patent drawing
  • US11574097B2 patent drawing

AI summary

Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.