Gate-Controlled Thyristor CAM Cell for High On/Off Search Matching
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Solution Overview
Problem
Conventional content-addressable memories (CAMs) using tunnel FETs with ambipolar transistors suffer from degraded performance, asymmetric junction profiles, and poor on/off current ratios, which affect sensing margin and data matching accuracy.
Innovation Solution
A gate-controlled thyristor configuration is introduced, comprising three transistors connected in series, with a charge trapping layer, allowing for ambipolar operation and high on/off current ratios, enabling accurate data matching through NFET and PFET states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a tunnel FET with symmetric source/drain junction design is used to achieve ambipolar property, then the transistor can exhibit different polarity properties, but the intrinsic TFET performance is degraded
Solution Approach 1:
The invention divides the single ambipolar transistor into three separate transistors (first NFET, second PFET, third NFET) connected in series. Each transistor has a dedicated function: the first and third transistors serve as switches controlled by search line voltages, while the second transistor stores data and provides ambipolar operation. This segmentation allows each transistor to be optimized for its specific function rather than requiring a single transistor to perform all functions, thereby resolving the contradiction between adaptability and reliability.
2Device complexity
If a single transistor with ambipolar property is used in CAM, then the device complexity is reduced, but the on/off current ratio becomes poor
Solution Approach 1:
The invention segments the single transistor design into three transistors connected in series, where the second transistor (PFET) provides the ambipolar switching function with high on/off current ratio, while the first and third transistors (NFETs) serve as controlled switches. This segmentation enables the system to achieve both low complexity in terms of cell structure and high reliability in terms of current ratio performance.
Solution Approach 2:
The invention applies different transistor types at different positions in the series connection: NFETs are used where high on-current is needed (first and third transistors), while a PFET is used where ambipolar switching with high off-state performance is required (second transistor). This local optimization of transistor types resolves the contradiction between device simplicity and current ratio performance.
3Reliability
If an asymmetric junction profile is used to achieve steep sub-threshold slope and high on-current, then the transistor performance is improved, but the ambipolar property is compromised
Solution Approach 1:
The invention segments the transistor functions so that the second transistor (PFET) can use an asymmetric junction profile optimized for steep sub-threshold slope and high on-current, while the first and third transistors (NFETs) provide the necessary ambipolar switching capability. This functional segmentation allows each transistor to be optimized for its specific role, resolving the contradiction between performance and adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The gate-controlled thyristor achieves a high on/off current ratio, enhancing sensing margin and data search accuracy, suitable for both NAND and NOR type CAM arrays.
Implementation Method 1
A gate-controlled thyristor configuration is introduced, comprising three transistors connected in series, with a charge trapping layer, allowing for ambipolar operation and high on/off current ratios
Data Source
AI summary
A gate-controlled thyristor (GCT) and CAM memory are provided. The GCT includes first, second and third transistors, each having a control end, first and second ends. The control ends of the first and second transistors are connected to a search line. The control end of the second transistor is applied with a fixed bias voltage, and the second end of the second transistor is connected to the first end of the first transistor. The second end of the third transistor is connected to the first end of the second transistor, and the first end is connected to a match line. Based on the search line voltage, a search bit is determined to compare the data and the search bit to determine whether the search bit matches the data. This configuration may be applied to 3D NAND memory, having a high capacity and performance.