Gate-to-Drain Clamp Circuit Layout for Power Device Breakdown Protection
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Solution Overview
Problem
Conventional semiconductor power device layouts with gate-to-drain (GD) clamping and electrostatic discharge (ESD) protection circuits face challenges such as increased die size, high leakage currents, and difficulty in controlling breakdown voltage, leading to higher production costs and performance issues.
Innovation Solution
A new layout combining gate-to-drain Zener diodes with a silicon diode and a small gate resistor, positioned on one side of the die, reduces die size and leakage current, while the parallel doped columns with a U-shaped bend and end well enhance breakdown voltage control, allowing for scalable low-voltage applications without additional manufacturing masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple gate-to-drain Zener diodes are placed at the periphery of the die, then breakdown protection is provided, but the die size increases and production cost increases
Solution Approach 1:
The patent combines the gate-to-drain Zener diode structure with the existing gate-to-source ESD diode structure, merging two protection functions into a unified layout. The Zener diodes are integrated within the same peripheral region where ESD diodes are already placed, eliminating the need for separate dedicated space for GD clamping.
Solution Approach 2:
The peripheral diode structure serves multiple functions simultaneously: it provides both gate-to-source ESD protection and gate-to-drain breakdown protection. The same physical structure and layout approach is used for both protection mechanisms, making the design universal and space-efficient.
2Reliability
If the width of gate to drain Zener diodes is increased, then breakdown protection capability is improved, but leakage current Idss increases significantly
Solution Approach 1:
The patent applies different doping characteristics and structural configurations to different regions of the diode structure. The Zener diodes are designed with specific local properties (doping concentration, junction depth) that optimize breakdown voltage while minimizing leakage. The end wells are selectively placed only at the ends of the diodes where high electric fields occur, providing localized field control without affecting the entire diode structure.
Solution Approach 2:
The patent carefully controls and optimizes key parameters including doping concentration, junction depth, and diode width to achieve the desired breakdown voltage while maintaining low leakage current. The end well depth and doping level are specifically tuned to suppress leakage at the high-field regions without compromising the overall breakdown protection capability.
3Reliability
If polysilicon diodes are used for GD clamping, then breakdown protection is achieved, but the polysilicon diodes occupy too much space
Solution Approach 1:
The patent employs standard silicon diode structures that can be formed using conventional CMOS processing techniques already present in the manufacturing line. These silicon-based structures are more space-efficient and easier to manufacture than polysilicon alternatives, providing a cost-effective and compact solution for breakdown protection.
4Manufacturing precision
If silicon diodes are used to supplement back-to-back polysilicon diodes, then breakdown voltage control is improved, but the device is limited to high breakdown voltage applications
Solution Approach 1:
The patent utilizes standard silicon diodes with conventional doping levels and junction depths that are compatible with mainstream CMOS technology. By optimizing the diode dimensions and doping profiles, the breakdown voltage can be precisely controlled for low-voltage applications (e.g., 5V, 12V, 24V) without requiring specialized high-voltage process modules, thus expanding adaptability across different application domains.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced die size, low leakage current, and well-controlled breakdown voltage, thereby reducing production costs and improving performance, particularly in low-voltage applications.
Implementation Method 1
The gate to drain clamping voltage is implemented with a plurality of Zener diodes in series connected to a silicon diode
Implementation Method 2
The back-to-back diodes are connected in series to a silicon diode which includes parallel doped columns in the semiconductor substrate
Data Source
AI summary
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.