Generation Lock for Multicore Data Structure Concurrency

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Solution Overview

Problem

In multitasking computing environments, existing synchronization methods like read/write semaphores limit concurrency and scalability due to resource-intensive cache line operations, especially when multiple CPU cores access shared data, leading to performance bottlenecks.

Innovation Solution

Implementing a generation lock mechanism that allows for efficient read and write operations by using a data structure with multiple generations, each with a unique identifier, enabling concurrent access and reducing the need for shared cache line transitions, thus enhancing scalability and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read/write semaphores are used to synchronize access to shared data, then data consistency is ensured, but concurrency is limited to a maximum of 2 to 4 CPU cores

Engineering Contradiction:
Improvedata consistencyVSAvoidconcurrency level
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the shared data structure into multiple cache lines, with each cache line protected by its own generation counter. This allows different CPU cores to access different cache lines concurrently without interfering with each other, thereby increasing the concurrency level from 2-4 cores to potentially all available cores in the system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces generation counters as intermediary variables in each cache line to mediate access control. Instead of using a centralized semaphore that blocks all access, each cache line independently tracks its generation state, allowing readers to proceed when generations match and writers to update generations atomically, thus maintaining consistency while enabling higher concurrency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a shared cache line is used for synchronization, then data consistency is maintained, but the system scalability is limited beyond an upper threshold

Engineering Contradiction:
Improvedata consistencyVSAvoidsystem scalability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent divides the previously monolithic shared cache line into multiple independent cache lines, each with its own generation counter. This segmentation allows the system to scale to more CPU cores because each cache line can be independently accessed, eliminating the single-point bottleneck and enabling linear scalability with the number of cores.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a generation counter dimension to each cache line, transforming the synchronization mechanism from a single shared resource into a multi-dimensional structure where each dimension (cache line) can be independently manipulated. This allows readers to check generation matches in one dimension while writers update in another, enabling concurrent operations that scale with system size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If frequent write operations are performed on shared memory, then data is kept up-to-date, but resource consumption increases due to cache line transitions

Engineering Contradiction:
Improvedata freshnessVSAvoidresource consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent performs preliminary actions by pre-incrementing the generation counter before writing data to the cache line. This allows readers to check the generation counter beforehand and only proceed with reading if the generation matches, avoiding unnecessary memory access and cache line transitions when data hasn't changed, thus reducing resource consumption while maintaining data freshness.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The generation counter in each cache line serves itself by automatically incrementing on write operations and providing its own validation mechanism for readers. This self-service approach eliminates the need for external synchronization overhead, allowing the cache line to manage its own consistency state efficiently, reducing overall system resource consumption while keeping data fresh.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10929201B2Method and system for implementing generation locks
Publication Date: 2021.02.23 WIND RIVER SYSTEMS INC
  • US10929201B2 patent drawing
  • US10929201B2 patent drawing
  • US10929201B2 patent drawing

AI summary

A system and method for implementing a generation lock for protecting a data structure is provide. The systems and methods synchronizes read and write transactions for a protected data structure in a multitasking environment and provides low latency and improved scalability. For example, a system and method for implementing a generation lock for protecting a data structure may be provided. The generation lock provides an improved mechanism for restricting access to a data structure that is typically read more often than written. Specifically, the generation lock provides a method for reading and writing to a protected data structures that has a low average latency as compared to traditional read/write semaphores. The generation lock also provides a mechanism in which the system is scalable, meaning that the addition of additional processor cores is capable of increasing the performance, e.g., rate of executing requests, of the system, and is not or is not substantially rate limited by a shared resource.