Variable Germanium Concentration Conductor for Memory Array Capacitive Coupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the formation of control gates for memory cells, particularly in three-dimensional memory arrays, there is a challenge in increasing capacitive coupling between the control gate and the charge-storage structure without increasing the size of the memory cell or select transistor, which limits memory density and performance.
Innovation Solution
The use of conductors with a variable concentration of germanium, where the concentration of germanium varies with the thickness of the conductor, allowing for controlled removal rates during formation, thereby creating a compositionally graded conductor that increases the surface area of the control gate without expanding the memory cell size, enhancing capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the surface area of the control gate is increased to improve capacitive coupling, then the capacitive coupling between control gate and charge-storage structure is improved, but the size of the memory cell increases
Solution Approach 1:
The patent introduces a vertical dimension to the control gate structure by forming a recess into the control gate along the vertical direction. This allows the control gate to extend deeper into the memory cell structure, increasing the surface area available for capacitive coupling with the charge-storage structure without increasing the lateral footprint of the memory cell. The recess enables three-dimensional utilization of space, effectively adding vertical coupling area while maintaining compact lateral dimensions.
Solution Approach 2:
The patent embeds the charge-storage structure within a recess formed in the control gate, creating a nested configuration where one structure is partially contained within another. The control gate recess surrounds a portion of the charge-storage structure, allowing the two components to be closely integrated in three-dimensional space. This nesting arrangement maximizes the interfacial contact area between the control gate and charge-storage structure while maintaining a compact overall cell size.
2Ease of manufacture
If the concentration of germanium is increased in the conductor to enhance removal rate control, then the removal rate during control gate formation is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by creating a compositionally graded conductor where the germanium concentration varies spatially within the conductor material. Specifically, the conductor has a first region with a first germanium concentration and a second region with a second germanium concentration. This spatial variation in composition allows different regions to exhibit different removal rates during etching processes, enabling precise control over the control gate formation without requiring complex external control mechanisms.
Solution Approach 2:
The patent utilizes parameter changes by systematically varying the germanium concentration parameter within the conductor material. The compositionally graded structure features a deliberate gradient in germanium content, where the concentration transitions from one value to another across different regions of the conductor. This parameter variation directly influences the etch removal rate, allowing the formation of control gates with specific depth profiles by controlling which regions are removed at different rates during the etching process.
Data Source
AI summary
An embodiment of a method of forming a portion of a memory array includes forming a conductor with a concentration of germanium that decreases with an increasing thickness of the conductor, removing a portion of the conductor at a rate governed by the concentration of germanium to form a tapered first opening through the conductor, removing a sacrificial material below the conductor to form a second opening contiguous with the tapered first opening, and forming a semiconductor in the contiguous first and second openings, wherein a portion of the semiconductor pinches off within the first opening adjacent an upper surface of the conductor before the contiguous first and second openings are completely filled with the semiconductor.