GIDL Current Generator Layout for Consistent 3D Memory Erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory devices face challenges in achieving reliable erase operations across varying numbers of programmed word lines, particularly in three-dimensional semiconductor memory devices, where the erase depth is inconsistent and may not be sufficient.
Innovation Solution
Incorporation of gate-induced drain leakage (GIDL) current generator circuits, both top and bottom, to enhance the erase operation by generating a higher current during the erase process, thereby improving the consistency and effectiveness of the erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory device structures are used for erase operations, then the device structure is simple, but the erase depth is inconsistent and insufficient across varying numbers of programmed word lines
Solution Approach 1:
The memory device is divided into multiple cell strings, each with dedicated select transistors and GIDL current generator circuits. This segmentation allows independent control and current generation for each cell string, ensuring consistent erase depth across all cells regardless of the number of programmed word lines.
Solution Approach 2:
GIDL current generator circuits are activated before the erase operation to pre-generate the required erase current. This preliminary action ensures that sufficient current is available at the start of the erase operation, achieving consistent erase depth across all memory cells.
2Adaptability or versatility
If the number of programmed word lines varies, then the memory device can store different amounts of data, but the erase depth becomes inconsistent
Solution Approach 1:
Each cell string is equipped with its own GIDL current generator circuit and select transistors, providing localized current generation and control. This local quality ensures that each cell string receives the necessary erase current independently, maintaining consistent erase depth regardless of how many word lines are programmed.
Solution Approach 2:
The erase operation utilizes parameter changes in the GIDL current generator circuits, adjusting voltage and current parameters to maintain consistent erase depth across varying numbers of programmed word lines. The circuits dynamically adapt current generation based on the specific erase requirements.
3Reliability
If higher erase current is generated to improve erase effectiveness, then the erase operation becomes more reliable, but the device complexity increases
Solution Approach 1:
The GIDL current generator circuits generate the erase current autonomously using the device's own voltage supplies and transistor structures. Each circuit self-regulates to produce the required current without external intervention, reducing the need for additional complex current control circuitry while maintaining reliable erase effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The GIDL current generator circuits facilitate a more reliable and efficient erase operation by generating sufficient current to effectively clear data from memory cells, regardless of the number of programmed word lines, enhancing the overall performance of three-dimensional memory devices.
Implementation Method 1
Incorporation of gate-induced drain leakage (GIDL) current generator circuits, both top and bottom, to enhance the erase operation by generating a higher current during the erase process
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.