Glass Array Substrate Layout for Narrow-Bezel LED Displays
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Solution Overview
Problem
Existing array substrates using FPC or PCB substrates suffer from warpage issues due to material expansion and contraction, affecting assembly and light-emitting performance, and when using a glass substrate, the narrow frame design and splicing gaps in display devices are compromised due to the need for side-edge traces.
Innovation Solution
An array substrate with a transparent rigid base, light-emitting chips, and a driving chip structure where the light-emitting surface faces the base, allowing direct arrangement of the driving wire layer and chip structure on the pins, eliminating the need for side-edge traces and enabling a narrow frame design and minimal splicing gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If FPC or PCB substrates are used for array substrates, then flexibility and electrical connection are improved, but warpage occurs due to material expansion and contraction
Solution Approach 1:
The patent changes the fundamental parameter of the substrate material from flexible (FPC/PCB) to rigid (glass), eliminating the thermal expansion and contraction issues that cause warpage. The glass substrate provides dimensional stability while maintaining electrical connectivity through alternative routing methods.
Solution Approach 2:
The patent transitions from planar trace routing on the substrate surface to three-dimensional routing where traces are formed on both the front and back surfaces of the glass substrate, and extend through via holes. This dimensional change allows electrical connections without requiring side-edge traces, solving the warpage problem while maintaining connectivity.
2Stability of the object's composition
If glass substrate is used, then warpage is prevented, but side-edge traces are required compromising narrow frame design
Solution Approach 1:
The patent uses three-dimensional routing where conductive traces are formed on both front and back surfaces of the glass substrate and connected through via holes. This eliminates the need for side-edge traces, enabling narrow frame designs while maintaining electrical connectivity across the array substrate.
Solution Approach 2:
The patent embeds via holes within the glass substrate to create internal electrical pathways. The traces on the front and back surfaces are nested within the three-dimensional structure of the substrate, allowing connections without extending to the edges, thus enabling narrower frames.
3Ease of manufacture
If light-emitting surface faces away from base, then conventional routing is possible, but splicing gaps increase and display quality decreases
Solution Approach 1:
The patent inverts the conventional arrangement by making the light-emitting surface face toward the glass substrate rather than away from it. This inversion allows the driving wire layer and driving chip structure to be arranged on the pins without obstructing the light-emitting surface, enabling precise splicing and narrow frame design while maintaining manufacturing feasibility through the three-dimensional routing approach.
Data Source
AI summary
An array substrate, a method of manufacturing the array substrate, and a display device are provided. The array substrate includes: a transparent rigid base; light-emitting chips on the transparent rigid base, each light-emitting chip including a chip body and a pin coupled to the chip body, a light-exiting surface of the chip body facing towards the transparent rigid base, and the pin being on a side of the chip body facing away from the transparent rigid base; a driving wire layer on a side of the pin facing away from the transparent rigid base; and a driving chip structure on a side of the driving wire layer facing away from the transparent rigid base. The driving chip structure is coupled to pins of the plurality of light-emitting chips through the driving wire layer, and is used for provide driving signals for the light-emitting chips.