Glass Interposer Bump Attach for Low-Temperature Die Bonding

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Solution Overview

Problem

Current solder-based chip attachment to a silicon layer is limited by in-plane heat transfer loss, especially for small dies, which results in reduced process and reliability windows due to higher surface area to volume ratio for heat loss, making it difficult to achieve solder melt at higher bond head and pedestal temperatures.

Innovation Solution

The use of a glass layer at the silicon layer level to enhance heat retention, combined with a silicon monoxide/silicon nitride material with lower thermal conductivity, allows for solder to melt at lower bond head and pedestal temperatures, and includes dummy routing and interconnects for mechanical and thermal stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If solder-based chip attachment is used on silicon layer, then electrical connection is achieved, but in-plane heat transfer loss prevents small dies from reaching solder melt temperature

Engineering Contradiction:
Improvesolder melt temperatureVSAvoidin-plane heat transfer loss
Core Design Contradiction:
TemperatureVSLoss of energy

Solution Approach 1:

A glass layer is introduced as an intermediary between the silicon layer and the small dies. This glass layer has lower thermal conductivity than silicon, acting as a thermal mediator that reduces in-plane heat transfer loss and helps retain heat at the bonding interface, enabling small dies to reach solder melt temperature.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the thermal conductivity parameter by replacing the silicon layer with a glass layer that has lower thermal conductivity. This parameter change reduces heat loss and allows the bonding process to succeed with small dies that previously could not reach the required temperature.

Inventive Principle:
Principle #35Parameter changes

2Temperature

If bond head temperatures and pedestal temperatures are increased to compensate for heat loss, then solder melting is achieved, but process and reliability window is reduced

Engineering Contradiction:
Improvebonding temperatureVSAvoidprocess and reliability window
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent converts the harmful effect of heat loss into a beneficial effect by using the glass layer's lower thermal conductivity to trap and retain heat at the bonding interface. This transforms what was previously a problem (heat loss requiring higher temperatures) into a solution (heat retention enabling lower temperatures with better process window).

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables lower bonding temperature processes, reduces temperature cycling failures, improves bonding density, and enhances assembly yield by maintaining heat within the microelectronics package, while providing mechanical stability and thermal insulation.

Implementation Method 1

A glass layer is introduced at the silicon layer level to enhance in-plane heat retention, using silicon monoxides/silicon nitrides with lower thermal conductivity

Methodology Applied
Scientific EffectThermal insulation: Thermal Insulation

Data Source

PatentUS12616026B2Permanent layer for bump chip attach
Publication Date: 2026.04.28 INTEL CORP
  • US12616026B2 patent drawing
  • US12616026B2 patent drawing
  • US12616026B2 patent drawing

AI summary

Disclosed herein are microelectronics package architectures utilizing glass layers and methods of manufacturing the same. The microelectronics packages may include a silicon layer, dies, and a glass layer. The silicon layer may include vias. The dies may be in electrical communication with vias. The glass layer may include interconnects in electrical communication with the vias.